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| rev. 1.4 october 2000 1/152 this is preliminary information on a new product in development or undergoing evaluation. details are subject to change without notice. st72c171 8-bit mcu with 8k flash, adc, wdg, spi, sci, timers spgas (software programmable gain amplifiers), op-amp product preview n memories C 8k of single voltage flash program memory with read-out protection C in-situ programming (remote isp) n clock, reset and supply management C enhanced reset system C low voltage supervisor (lvd) with 3 program- mable levels C low consumption resonator or rc oscillators (internal or external) and by-pass for external clock source, with safe control capabilities C 3 power saving modes n 22 i/o ports C 22 multifunctional bidirectional i/o lines: C 16 interrupt inputs on 2 independent lines C 8 lines configurable as analog inputs C 20 alternate functions Cemi filtering n 2 timers and watchdog C one 16-bit timer with: 2 input captures, 2 output compares, external clock input, pwm and pulse generator modes C one 8-bit autoreload timer (art) with: 2 pwm output channels (internally connectable to the spga inputs), 1 input capture, external clock input C configurable watchdog (wdg) n 2 communications interfaces C synchronous serial peripheral interface (spi) C serial communications interface (sci) n 3 analog peripherals C 2 software programmable gain operational amplifiers (spgas) with rail-to-rail input and output, v dd independent (band gap) and pro- grammable reference voltage (1/8 v dd reso- lution), offset compensation, dac & on/off switching capability C 1 rail-to-rail input and output op-amp C 8-bit a/d converter with up to 11 channels (in- cluding 3 internal channels connected to the op-amp & spga outputs) n instruction set C 8-bit data manipulation C 63 basic instructions C 17 main addressing modes C 8 x 8 unsigned multiply instruction C true bit manipulation n development tools C full hardware/software development package device summary so34 psdip32 features st72c171k2m st72c171k2b flash - bytes 8k single voltage ram (stack) - bytes 256 (128) peripherals 2 spgas, 1 op-amp, watchdog, 3 timers, spi, sci, adc (11 chan.) 2 spgas, watchdog, 3 timers, spi, sci, adc (11 chan.) operating supply 3.2 v to 5.5 v cpu frequency up to 8 mhz (with up to 16 mhz oscillator) temperature range - 40c to + 85c package so34 psdip32 1
table of contents 152 2/152 1 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 structural organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 in-situ programming (isp) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 memory read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 clock, reset and supply register description . . . . . . . . . . . . . . . . . . . . . . 23 5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 op-amp module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.5 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.6 pwm auto-reload timer (art) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.7 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.8 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.9 8-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table of contents 3/152 9 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.10 timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.11 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.12 8-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.13 op-amp module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 10.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 10.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.3 soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.4 package/socket footprint proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . 147 11.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.2 device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 11.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.5 to get more information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 st72c171 4/152 1 general description 1.1 introduction the st72c171 is a member of the st7 family of microcontrollers. all devices are based on a com- mon industry-standard 8-bit core, featuring an en- hanced instruction set. the st72c171 features single-voltage flash memory with byte-by-byte in-situ programming (isp) capability. under software control, the device can be placed in wait, slow, or halt mode, reducing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes the device includes a low consumption and fast start on-chip oscillator, cpu, flash pro- gram memory, ram, 22 i/o lines and the following on-chip peripherals: analog-to-digital converter (adc) with 8 multiplexed analog inputs, op-amp module, synchronous spi serial interface, asyn- cronous serial interface (sci), watchdog timer, a 16-bit timer featuring external clock input, pulse generator capabilities, 2 input captures and 2 output compares, an 8-bit timer featuring exter- nal clock input, pulse generator capabilities (2 channels), autoreload and input capture. the op-amp module adds on-chip analog fea- tures to the mcu, that usually require using exter- nal components. figure 1. st72c171 block diagram address and data bus oscin oscout reset 16-bit timer 8-bit adc port b watchdog internal clock control 256b-ram pa[7:0] v ss v dd power supply 8k flash port a pwm/art timer spi pb[7:0] lvd sci multiosc + clock filter op-amp v ssa v dda 8-bit core alu port c pc[5:0] oa1out oa2out memory oa3out* *only on 34-pin devices oa3pin* st72c171 5/152 1.2 pin description figure 2. 34-pin so package pinout figure 3. 32-pin sdip package pinout pc2 / oa1pin / pwm0r pc3 / oa1nin oa1out pc4 / mco/ oa3nin v dda v ssa oa3out pc5/ pwm0 pa7 / ain7 / pwm1 pa6 / ain6 / articp0 pa5 / ain5 pa4 / ain4 / ocmp1 pa3 / ain3 / ocmp2 pa2 / ain2 / icap1 pa1 / ain1 / icap2 pa0 / ain0 reset 21 22 23 24 25 26 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 oa2out pwm1r / oa2pin / pc1 oa2nin / pc0 oa3pin tdo / pb7 rdi / pb6 ispdata / miso / pb5 mosi / (hs) pb4 ispclk / sck / (hs) pb3 ss / (hs) pb2 artclk / (hs) pb1 extclk / (hs) pb0 v dd v ss osc2 osc1 ispsel 15 16 17 20 19 18 ei1 ei0 (hs) 20ma high sink capability oa2out pwm1r / oa2pin / pc1 oa2nin / pc0 tdo / pb7 rdi / pb6 ispdata / miso / pb5 mosi / (hs) pb4 ispclk / sck/ (hs) pb3 ss / (hs) pb2 artclk / (hs) pb1 extclk / (hs) pb0 v dd v ss osc2 osc1 ispsel pc2 / oa1pin / pwm0r pc3 / oa1nin oa1out pc4 / mco v dda v ssa pc5 / pwm0 pa7 / ain7 / pwm1 pa6 / ain6 /articp0 pa5 / ain5 pa4 / ain4 / ocmp1 pa3 / ain3 / ocmp2 pa2 / ain2 / icap1 pa1 / ain1 / icap2 pa0 / ain0 reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ei1 ei0 (hs) 20ma high sink capability st72c171 6/152 pin description (contd) legend / abbreviations: type: i = input, o = output, s = supply in/output level: c = cmos 0.3v dd /0.7v dd , c r = cmos levels with resistive output (1k) a = analog levels output level: hs = high sink (on n-buffer only), port configuration capabilities: C input:float = floating, wpu = weak pull-up, int = interrupt, ana = analog C output: od = open drain, t = true open drain, pp = push-pull note: the reset configuration of each pin is shown in bold. table 1. device pin description pin n pin name type level port main function (after reset) alternate function sdip32 so34 input output input output float wpu int ana od pp 1 1 oa2out o a oa2 output 22 pc1/oa2pin/ pwm1r i/o c c/c r x x x x x port c1 oa2 noninverting input and/or art pwm1 resistive output 3 3 pc0/oa2nin i/o c/a c x x x x x port c0 oa2 inverting input - 4 oa3pin i a oa3 noninverting input 4 5 pb7/tdo i/o c x ei1 x x port b7 sci transmit 5 6 pb6/rdi i/o c x ei1 x x port b6 sci receive 6 7 pb5/miso/ispdata i/o c x ei1 x x port b5 spi data master in/slave out or in situ programming data in- put 7 8 pb4/mosi i/o c hs x ei1 x x port b4 spi data master out/slave in 8 9 pb3/sck/ispclk i/o c hs x ei1 x x port b3 spi clock or in situ program- ming clock output 910pb2/ss i/o c hs x ei1 x x port b2 spi slave select (active low) 10 11 pb1/artclk i/o c hs x ei1 x x port b1 art external clock 11 12 pb0/extclk i/o c hs x ei1 x x port b0 timer16 external clock 12 13 v dd s digital main supply voltage 13 14 v ss s digital ground voltage 14 15 osc2 resonator oscillator inverter output or capaci- tor input for rc oscillator 15 16 osc1 external clock input or resonator oscillator in- verter input or resistor input for rc oscillator 16 17 ispsel i c in situ programming mode select must be tied to v ss in user mode 17 18 reset i/o c x x external reset 18 19 pa0/ain0 i/o c x ei0 x x x port a0 adc input 0 19 20 pa1/ain1/icap2 i/o c x ei0 x x x port a1 adc input 1 ortimer16 input capture 2 st72c171 7/152 notes : 1. in the interrupt input column, eix defines the associated external interrupt vector. if the weak pull-up column (wpu) is associated with the interrupt column (int), then the i/o configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. osc1 and osc2 pins connect a crystal or ceramic resonator, an external rc, or an external source to the on-chip oscillator see dedicated see pin description on page 5. for more details. 20 21 pa2/ain2/icap1 i/o c x ei0 x x x port a2 adc input 2 or timer16 input capture 1 21 22 pa3/ain3/ocmp2 i/o c x ei0 x x x port a3 adc input 3 or timer16 output compare 2 22 23 pa4 /ain4/ocmp1 i/o c x ei0 x x x port a4 adc input 4 or timer16 output compare 1 23 24 pa5/ain5 i/o c x ei0 x x x port a5 adc input 5 24 25 pa6/ain6/articp0 i/o c x ei0 x x x port a6 adc input 6 or art input cap- ture 25 26 pa7/ain7/pwm1 i/o c x ei0 x x x port a7 adc input 7 or art pwm1 output 26 27 pc5 / pwm0 i/o c x x x x port c5 art pwm0 output - 28 oa3out o a oa3 output 27 29 v ssa analog ground 28 30 v dda analog supply 29 31 pc4/mco/oa3nin i/o c x x x x port c4 main clock out or oa3 invert- ing input 30 32 oa1out o a oa1 output 31 33 pc3/oa1nin i/o c/a c x x x x port c3 oa1 inverting input 32 34 pc2/oa1pin/ pwm0r i/o c/a c/c r x x x x port c2 oa1 non-inverting input and/ or art pwm0 resistive output pin n pin name type level port main function (after reset) alternate function sdip32 so34 input output input output float wpu int ana od pp st72c171 8/152 1.3 memory map 1.3.1 introduction figure 4. program memory map short addressing ram stack 0100h 017fh 0080h 00ffh 0000h 8 kbytes interrupt & reset vectors hw registers 017fh 0080h 007fh 0180h dfffh reserved (see table 1.3.2 ) e000h ffdfh ffe0h ffffh (see table 4 ) 256 bytes ram flash (128 bytes) (128 bytes) zero page st72c171 9/152 1.3.2 data register table 2. hardware register memory map address block name register label register name reset status remarks 0000h 0001h 0002h 0003h port a padr paddr paor data register data direction register option register not used 00h 00h 00h r/w r/w r/w absent 0004h 0005h 0006h 0007h port b pbdr pbddr pbor data register data direction register option register not used 00h 00h 00h r/w r/w r/w absent 0008h 0009h 000ah port c pcdr pcddr pcor data register data direction register option register 00h 00h 00h r/w r/w r/w 000bh to 001ah reserved area (16 bytes) 001bh 001ch 001dh 001eh 001fh opamp oa1cr oa2cr oa3cr oairr oavrcr oa1 control register oa2 control register oa3 control register oa interrupt & readout register oa voltage reference control register 00h 00h 00h 00h 00h r/w r/w r/w section 7.3 r/w 0020h misc1 miscr1 miscellaneous register 1 00h see section 4.3.5 0021h 0022h 0023h spi spidr spicr spisr data i/o register control register status register xxh 0xh 00h r/w r/w read only 0024h wdg wdgcr watchdog control register 7fh r/w 0025h crs crsr clock, reset and supply control / status register 00h r/w 0026h to 0030h reserved area (11 bytes) 0031h 0032h 0033h 0034h- 0035h 0036h- 0037h 0038h- 0039h 003ah- 003bh 003ch- 003dh 003eh- 003fh timer16 tacr2 tacr1 tasr taic1hr taic1lr taoc1hr taoc1lr tachr taclr taachr taaclr taic2hr taic2lr taoc2hr taoc2lr control register2 control register1 status register input capture1 high register input capture1 low register output compare1 high register output compare1 low register counter high register counter low register alternate counter high register alternate counter low register input capture2 high register input capture2 low register output compare2 high register output compare2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h misc2 miscr2 miscellaneous register2 00h see section 7.2.2 st72c171 10/152 0041h to 004fh reserved area (15 bytes) 0050h 0051h 0052h 0053h 0054h sci scisr scidr scibrr scicr1 scicr2 status register data register baud rate register control register 1 control register 2 0c0h 0xxh 0xxh 0xxh 00h read only r/w r/w r/w r/w 0055h to 006fh reserved area (27 bytes) 0070h 0071h adc adcdr adccsr data register control/status register 00h 00h read only r/w 0072h 0073h reserved area (2 bytes) 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh art/pwm pwmdcr1 pwmdcr0 pwmcr artcsr artcar artarr articcsr articr1 pwm duty cycle register 1 pwm duty cycle register 0 pwm control register control/status register counter access register auto reload register input capture control status register input capture register 1 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w read only 007ch to 007fh reserved area (4 bytes) address block name register label register name reset status remarks st72c171 11/152 2 flash program memory 2.1 introduction flash devices have a single voltage non-volatile flash memory that may be programmed in-situ (or plugged in a programming tool) on a byte-by- byte basis. 2.2 main features n remote in-situ programming (isp) mode n up to 16 bytes programmed in the same cycle n mtp memory (multiple time programmable) n read-out memory protection against piracy 2.3 structural organisation the flash program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants. the flash program memory is mapped in the up- per part of the st7 addressing space and includes the reset and interrupt user vector area . 2.4 in-situ programming (isp) mode the flash program memory can be programmed using remote isp mode. this isp mode allows the contents of the st7 program memory to be up- dated using a standard st7 programming tools af- ter the device is mounted on the application board. this feature can be implemented with a minimum number of added components and board area im- pact. an example remote isp hardware interface to the standard st7 programming tool is described be- low. for more details on isp programming, refer to the st7 programming specification. remote isp overview the remote isp mode is initiated by a specific se- quence on the dedicated ispsel pin. the remote isp is performed in three steps: C selection of the ram execution mode C download of remote isp code in ram C execution of remote isp code in ram to pro- gram the user program into the flash remote isp hardware configuration in remote isp mode, the st7 has to be supplied with power (v dd and v ss ) and a clock signal (os- cillator and application crystal circuit for example). this mode needs five signals (plus the v dd signal if necessary) to be connected to the programming tool. this signals are: C reset : device reset Cv ss : device ground power supply C ispclk: isp output serial clock pin C ispdata: isp input serial data pin C ispsel: remote isp mode selection. this pin must be connected to v ss on the application board through a pull-down resistor. if any of these pins are used for other purposes on the application, a serial resistor has to be imple- mented to avoid a conflict if the other device forces the signal level. figure 1 shows a typical hardware interface to a standard st7 programming tool. for more details on the pin locations, refer to the device pinout de- scription. figure 5. typical remote isp interface 2.5 memory read-out protection the read-out protection is enabled through an op- tion bit. for flash devices, when this option is selected, the program and data stored in the flash memo- ry are protected against read-out piracy (including a re-write protection). when this protection option is removed the entire flash program memory is first automatically erased. however, the e 2 prom data memory (when available) can be protected only with rom devices. ispsel v ss reset ispclk ispdata osc1 osc2 v dd st7 he10 connector type to programming tool 10k w c l0 c l1 application 47k w 1 xtal st72c171 12/152 3 central processing unit 3.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 3.2 main features n 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes n two 8-bit index registers n 16-bit stack pointer n low power modes n maskable hardware interrupts n non-maskable software interrupt 3.3 cpu registers the 6 cpu registers shown in figure 1 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 6. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value st72c171 13/152 cpu registers (contd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask . this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptable because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the bit test and branch, shift and rotate instructions. 70 111hinzc st72c171 14/152 central processing unit (contd) stack pointer (sp) read/write reset value: 01 7fh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 7 ). since the stack is 128 bytes deep, the 10 most sig- nificant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp5 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 7 . C when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. C on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 7. stack manipulation example 15 8 00000001 70 0 1 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 017fh @ 0100h stack higher address = 017fh stack lower address = 0100h st72c171 15/152 4 supply, reset and clock management the device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. an overview is shown in figure 8 . 4.1 main features n supply manager C main supply low voltage detection (lvd) C global power down n reset sequence manager (rsm) n multi-oscillator (mo) C 4 crystal/ceramic resonator oscillators C 2 external rc oscillators C 1 internal rc oscillator n clock security system (css) Cclock filter C backup safe oscillator n main clock controller (mcc) figure 8. clock, reset and supply block diagram ie sod 0 - - - rf rf crsr css - wdg f osc main clock controller (mcc) cf interrupt lvd low voltage detector (lvd) multi- oscillator (mo) f cpu from watchdog peripheral mco oscout oscin reset v dd v ss reset sequence manager (rsm) clock filter safe osc clock security system (css) st72c171 16/152 4.2 low voltage detector (lvd) to allow the integration of power management features in the application, the low voltage detec- tor function (lvd) generates a static reset when the v dd supply voltage is below a v it- reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v it- reference value for a voltage drop is lower than the v it+ reference value for power-on in order to avoid a parasitic reset when the mcu starts run- ning and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: Cv it+ when v dd is rising Cv it- when v dd is falling the lvd function is illustrated in the figure . provided the minimum v dd value (guaranteed for the oscillator frequency) is above v it- , the mcu can only be in two modes: C under full software control C in static safe reset in these conditions, secure operation is always en- sured for the application without the need for ex- ternal reset hardware. during a low voltage detector reset, the r eset pin is held low, thus permitting the mcu to reset other devices. notes : 1. the lvd allows the device to be used without any external reset circuitry. 2. three different reference levels are selectable through the option byte according to the applica- tion requirement. lvd application note application software can detect a reset caused by the lvd by reading the lvdrf bit in the crsr register. this bit is set by hardware when a lvd reset is generated and cleared by software (writing zero). figure 9. low voltage detector vs reset v dd v it+ reset v it- v hyst st72c171 17/152 4.2.1 reset sequence manager (rsm) the rsm block of the cross module includes three reset sources as shown in figure 10 : n external reset source pulse n internal lvd reset (low voltage detection) n internal watchdog reset these sources act on the reset pin and it is al- ways kept low during the read option reset phase. the reset service routine vector is fixed at the fffeh-ffffh addresses in the st7 memory map. figure 10. reset block diagram the basic reset sequence consists of 4 phases as shown in figure 11 : n option byte reading to configure the device n delay depending on the reset source n 4096 cpu clock cycle delay n reset vector fetch the duration of the option byte reading phase (t rob ) is defined in the electrical characteristics section. this first phase is initiated by an external reset pin pulse detection, a watchdog r eset detection, or when v dd rises up to v lvdopt . the 4096 cpu clock cycle delay allows the oscilla- tor to stabilise and to ensure that recovery has tak- en place from the reset state. the reset vector fetch phase duration is 2 clock cycles. figure 11. reset sequence phases f cpu counter reset r on v dd watchdog reset lvd reset internal reset read option reset reset read option byte internal reset 4096 clock cycles fetch vector delay t rob st72c171 18/152 reset sequence manager (contd) 4.2.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristics section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized. this detection is asynchro- nous and therefore the mcu can enter reset state even in halt mode. the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. two reset s equences can be associated with this reset source: short or long external reset pulse (see figure 12 ). starting from the external reset pulse recogni- tion, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . 4.2.3 internal low voltage detection reset two different reset s equences caused by the in- ternal lvd circuitry can be distinguished: n power-on reset n voltage drop r eset the device reset pin acts as an output that is pulled low when v dd st72c171 20/152 multioscillator (mo) (contd) external rc oscillator this oscillator allows a low cost solution on the main clock of the st7 using only an external resis- tor and an external capacitor (see figure 15 ). the selection of the external rc oscillator has to be done by option byte. the frequency of the external rc oscillator is fixed by the resistor and the capacitor values: the previous formula shows that in this mo mode, the accuracy of the clock is directly linked to the accuracy of the discrete components. figure 15. mo external rc internal rc oscillator the internal rc oscillator mode is based on the same principle as the external rc one including the an on-chip resistor and capacitor. this mode is the most cost effective one with the drawback of a lower frequency accuracy. its frequency is in the range of several mhz. in this mode, the two oscillator pins have to be tied to ground as shown in figure 16 . the selection of the internal rc oscillator has to be done by option byte. figure 16. mo internal rc f osc ~ n r ex . c ex oscin oscout st7 c ex r ex oscin oscout st7 st72c171 21/152 4.3 clock security system (css) the clock security system (css) protects the st7 against main clock problems. to allow the in- tegration of the security features in the applica- tions, it is based on a clock filter control and an in- ternal safe oscillator. the css can be enabled or disabled by option byte. 4.3.1 clock filter control the clock filter is based on a clock frequency limi- tation function. this filter function is able to detect and filter high frequency spikes on the st7 main clock. if the oscillator is not working properly (e.g. work- ing at a harmonic frequency of the resonator), the current active oscillator clock can be totally fil- tered, and then no clock signal is available for the st7 from this oscillator anymore. if the original clock source recovers, the filtering is stopped au- tomatically and the oscillator supplies the st7 clock. 4.3.2 safe oscillator control the safe oscillator of the css block is a low fre- quency back-up clock source (see figure 17 ). if the clock signal disappears (due to a broken or disconnected resonator...) during a safe oscillator period, the safe oscillator delivers a low frequency clock signal which allows the st7 to perform some rescue operations. automatically, the st7 clock source switches back from the safe oscillator if the original clock source recovers. limitation detection the automatic safe oscillator selection is notified by hardware setting the cssd bit of the crsr register. an interrupt can be generated if the cs- sie bit has been previously set. these two bits are described in the crsr register description. 4.3.3 low power modes 4.3.4 interrupts the css interrupt event generates an interrupt if the corresponding enable control bit (cssie) is set and the interrupt mask in the cc register is re- set (rim instruction). note 1: this interrupt allows to exit from active-halt mode if this mode is available in the mcu. figure 17. clock filter function and safe oscillator function mode description wait no effect on css. css interrupt cause the device to exit from wait mode. halt the crsr register is frozen. the css (in- cluding the safe oscillator) is disabled until halt mode is exited. the previous css configuration resumes when the mcu is woken up by an interrupt with exit from halt mode capability or from the counter reset value when the mcu is woken up by a reset. interrupt event event flag enable control bit exit from wait exit from halt 1) css event detection (safe oscillator acti- vated as main clock) cssd cssie yes no f osc /2 f cpu f osc /2 f cpu f sfosc safe oscillator function clock filter function st72c171 22/152 4.3.5 main clock controller (mcc) the mcc block supplies the clock for the st7 cpu and its internal peripherals. it allows the pow- er saving modes such as slow mode to be man- aged by the application. all functions are managed by the miscellaneous register 1 (miscr1). the mcc block consists of: C a programmable cpu clock prescaler C a clock-out signal to supply external devices the prescaler allows the selection of the main clock frequency and is controlled with three bits of the miscr1: cp1, cp0 and sms. the clock-out capability is an alternate function of an i/o port pin, providing the f cpu clock as an out- put for driving external devices. it is controlled by the mco bit in the miscr1 register. figure 18. main clock controller (mcc) block diagram div 2, 4, 8, 16 div 2 sms cp1 cp0 cpu clock miscr1 to cpu and peripherals f osc mco port function alternate oscout oscin multi- oscillator (mo) clock filter (cf) mco f cpu st72c171 23/152 4.4 clock, reset and supply register description clock reset and supply register (crsr) read/write reset value: 000x 000x (00h) bit 7:5 = reserved. bit 4 = lvdrf lvd reset flag this bit indicates when set that the last reset was generated by the lvd block. it is set by hardware (lvd reset) and cleared by software (writing zero) or a watchdog reset. see wdgrf flag descrip- tion for more details. bit 3 = reserved. bit 2 = cssie css interrupt enable this bit allows to enable the interrupt when a dis- trurbance is detected by the clock security sys- tem (cssd bit set). it is set and cleared by soft- ware. 0: clock filter interrupt disable 1: clock filter interrupt enable bit 1 = cssd css safe osc. detection this bit indicates that the safe oscillator of the css block has been selected. it is set by hardware and cleared by reading the crsr register when the original oscillator recovers. 0: safe oscillator is not active 1: safe oscillator has been activated bit 0 = wdgrf watchdog reset flag this bit indicates when set that the last reset was generated by the watchdog peripheral. it is set by hardware (watchdog reset) and cleared by soft- ware (writing zero) or an lvd reset. combined with the lvdrf flag information, the flag description is given by the following table. table 3. supply, reset and clock register map and reset values 70 --- lvd rf - css ie css d wdg rf reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lvd 1 x address (hex.) register label 76543210 0020h miscr reset value pei3 0 pei2 0 mco 0 pei1 0 pei0 0 cp1 0 cp0 0 sms 0 0025h crsr reset value - 0 - 0 - 0 lvdrf x - 0 cssie 0 cssd 0 wdgrf x st72c171 24/152 5 interrupts the st7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the interrupt mapping table and a non- maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 19 . the maskable interrupts must be enabled clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsec- tion). when an interrupt has to be serviced: C normal processing is suspended at the end of the current instruction execution. C the pc, x, a and cc registers are saved onto the stack. C the i bit of the cc register is set to prevent addi- tional interrupts. C the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the interrupt mapping table for vector address- es). the interrupt service routine should finish with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared and the main program will resume. priority management by default, a servicing interrupt cannot be inter- rupted because the i bit is set by hardware enter- ing in interrupt routine. in the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the interrupt map- ping table). interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specifi- cally mentioned interrupts allow the processor to leave the halt low power mode (refer to the exit from halt column in the interrupt mapping ta- ble). 5.1 non maskable software interrupt this interrupt is entered when the trap instruc- tion is executed regardless of the state of the i bit. it will be serviced according to the flowchart on figure 19 . 5.2 external interrupts external interrupt vectors can be loaded into the pc register if the corresponding external interrupt occurred and if the i bit is cleared. these interrupts allow the processor to leave the halt low power mode. the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). an external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins, connected to the same inter- rupt vector, are configured as interrupts, their sig- nals are logically anded before entering the edge/ level detection block. caution: the type of sensitivity defined in the mis- cellaneous or interrupt register (if available) ap- plies to the ei source. in case of an anded source (as described on the i/o ports section), a low level on an i/o pin configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity. 5.3 peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: C the i bit of the cc register is cleared. C the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: C writing 0 to the corresponding bit in the status register or C access to the status register while the flag is set followed by a read or write of an associated reg- ister. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed. st72c171 25/152 interrupts (contd) figure 19. interrupt processing flowchart i bit set? y n iret? y n from reset load pc from interrupt vector stack pc, x, a, cc set i bit fetch next instruction execute instruction this clears i bit by default restore pc, x, a, cc from stack interrupt y n pending? st72c171 26/152 interrupts (contd) table 4. interrupt mapping source block description register label flag exit from halt vector address priority order reset reset n/a n/a yes fffeh-ffffh trap software n/a n/a no fffch-fffdh ei0 ext. interrupt ei0 n/a n/a yes fffah-fffbh ei1 ext. interrupt ei1 n/a n/a yes fff8h-fff9h css clock filter interrupt crsr cssd no fff6h-fff7h spi transfer complete spisr spif no fff4h-fff5h mode fault modf timer 16 input capture 1 tasr icf1_1 no fff2h-fff3h output compare 1 ocf1_1 input capture 2 icf2_1 output compare 2 ocf2_1 timer overflow tof_1 art/pwm input capture 1 articcsr icf0 yes fff0h-fff1h timer overflow artcsr ovf ffeeh-ffefh op-amp oa1 interrupt oirr oa1v yes ffech-ffedh oa2 interrupt oa2v ffeah-ffebh not used ffe6-ffe9 sci sci peripheral interrupts no ffe4-ffe5 not used ffe0h-ffe3h highest priority priority lowest st72c171 27/152 6 power saving modes 6.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, three main power saving modes are implemented in the st7 (see figure 20 ). after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the the oscil- lator status. figure 20. power saving mode transitions 6.2 slow mode this mode has two targets: C to reduce power consumption by decreasing the internal clock in the device, C to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by three bits in the miscr1 register: the sms bit which enables or disables slow mode and two cpx bits which select the internal slow frequency (f cpu ). in this mode, the oscillator frequency can be divid- ed by 4, 8, 16 or 32 instead of 2 in normal operat- ing mode. the cpu and peripherals are clocked at this lower frequency. note: slow-wait mode is activated when enter- ring the wait mode while the device is already in slow mode. figure 21. slow mode clock transitions power consumption wait slow run halt high low slow wait 00 01 sms cp1:0 f cpu new slow normal run mode miscr1 frequency request request f osc /2 f osc /4 f osc /8 f osc /2 st72c171 28/152 power saving modes (contd) 6.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the wfi st7 software instruction. all peripherals remain active. during wait mode, the i bit of the cc register are forced to 0, to ena- ble all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereup- on the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 22 . figure 22. wait mode flow-chart note: before servicing an interrupt, the cc regis- ter is pushed on the stack. the i bit of the cc reg- ister is set during the interrupt routine and cleared when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals i bit on on 0 off fetch reset vector or service interrupt cpu oscillator peripherals i bit on off 1 on cpu oscillator peripherals i bit (see note) on on 1 on 4096 cpu clock cycle delay st72c171 29/152 power saving modes (contd) 6.4 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the st7 halt instruction (see figure 24 ). the mcu can exit halt mode on reception of ei- ther an specific interrupt (see table 4, interrupt mapping, on page 26) or a r eset. w hen exiting halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and the 4096 cpu cycle delay is used to stabilize the os- cillator. after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 23 ). when entering halt mode, the i bit in the cc reg- ister is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes immedi- ately. in the halt mode the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). the compatibility of watchdog operation with halt mode is configured by the wdghalt op- tion bit of the option byte. the halt instruction when executed while the watchdog system is en- abled, can generate a watchdog reset (see section 11.1 option bytes for more details). figure 23. halt mode timing overview figure 24. halt mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec- tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). re- fer to table 4, interrupt mapping, on page 26 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. halt run run 4096 cpu cycle delay reset or interrupt halt instruction fetch vector halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i bit off off 0 off fetch reset vector or service interrupt cpu oscillator peripherals i bit on off 1 on cpu oscillator peripherals i bit 4) on on 1 on 4096 cpu clock cycle delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 st72c171 30/152 7 on-chip peripherals 7.1 i/o ports 7.1.1 introduction the i/o ports offer different functional modes: C transfer of data through digital inputs and outputs and for specific pins: C analog signal input (adc) C alternate signal input/output for the on-chip pe- ripherals. C external interrupt generation an i/o port is composed of up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital out- put. 7.1.2 functional description each port is associated to 2 main registers: C data register (dr) C data direction register (ddr) and some of them to an optional register (see reg- ister description): C option register (or) each i/o pin may be programmed using the corre- sponding register bits in ddr and or registers: bit x corresponding to pin x of the port. the same cor- respondence is used for the dr register. the following description takes into account the or register, for specific ports which do not provide this register refer to the i/o port implementation section 7.1.2.5 . the generic i/o block diagram is shown on figure 26 . 7.1.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. notes : 1. all the inputs are triggered by a schmitt trigger. 2. when switching from input mode to output mode, the dr register should be written first to output the correct value as soon as the port is con- figured as an output. interrupt function when an i/o is configured in input with interrupt, an event on this i/o can generate an external in- terrupt request to the cpu. the interrupt sensitivi- ty is given independently according to the descrip- tion mentioned in the miscellaneous register or in the interrupt register (where available). each pin can independently generate an interrupt request. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see interrupts sec- tion). if more than one input pin is selected simul- taneously as interrupt source, this is logically ored. for this reason if one of the interrupt pins is tied low, it masks the other ones. 7.1.2.2 output mode the pin is configured in output mode by setting the corresponding ddr register bit. in this mode, writing 0 or 1 to the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. note : in this mode, the interrupt function is disa- bled. 7.1.2.3 digital alternate function when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin has to be configured in input mode. in this case, the pins state is also digitally readable by addressing the dr register. notes: 1. input pull-up configuration can cause an unex- pected value at the input of the alternate peripher- al input. 2. when the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (ddr = 0). warning : the alternate function must not be acti- vated as long as the pin is configured as input with interrupt, in order to avoid generating spurious in- terrupts. st72c171 31/152 i/o ports (contd) 7.1.2.4 analog alternate function when the pin is used as an adc input the i/o must be configured as input, floating. the analog multi- plexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maximum ratings. 7.1.2.5 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific feature of the i/o port such as adc in- put (see figure 26 ) or true open drain. switching these i/o ports from one state to another should be done in a sequence that prevents unwanted side effects. recommended safe transitions are il- lustrated in figure 25 . other transitions are poten- tially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 25. recommended i/o state transition diagram with interrupt input output no interrupt input push-pull open-drain output st72c171 32/152 i/o ports (contd) figure 26 . i/o block diagram table 5. port mode configuration legend: 0 - present, not activated 1 - present and activated notes: C no or register on some ports (see register map). C adc switch on ports with analog alternate functions. dr ddr latch latch data bus dr sel ddr sel v dd pad analog switch analog enable (adc) m u x alternate alternate alternate enable common analog rail alternate m u x alternate input pull-up (s ee t able below ) output p-buffer (s ee t able b elow ) n-buffer 1 0 1 0 or latch or sel from other bits external pull-up condition enable enable gnd (s ee t able below ) (s ee n ote below ) cmos schmitt trigger source (eix) interrupt sensitivity sel configuration mode pull-up p-buffer floating 0 0 pull-up 1 0 push-pull 0 1 true open drain not present not present open drain (logic level) 0 0 st72c171 33/152 i/o ports (contd) 7.1.2.6 device specific configurations table 6. port configuration *reset state. port pin name input (ddr =0) output (ddr=1) or = 0 or = 1 or = 0 or = 1 port a pa7: pa0 floating* pull-up with interrupt open drain push-pull port b pb0:pb4 floating* pull-up with interrupt open drain high sink capability push-pull pb5:pb7 floating* pull-up with interrupt open drain push-pull port c pc0:pc5 floating* pull-up open drain push-pull st72c171 34/152 i/o ports (contd) 7.1.3 register description data registers port a data register (padr) port b data register (pbdr) port c data register (pcdr) read/write reset value: 0000 0000 (00h) bit 7:0 = d[7:0] data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken in account even if the pin is configured as an input. reading the dr register returns either the dr register latch content (pin configured as output) or the digital val- ue applied to the i/o pin (pin configured as input). data direction registers port a data direction register (paddr) port b data direction register (pbddr) port c data direction register (pcddr) read/write reset value: 0000 0000 (00h) (input mode) bit 7:0 = dd[7:0] data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bits is set and cleared by software. 0: input mode 1: output mode option registers port a option register (paor) port b option register (pbor) port c option register (pcor) read/write reset value: 0000 0000 (00h) (no interrupt) bit 7:0 = o[7:0] option register 8 bits. the paor, pbor and pcor registers are used to select pull-up or floating configuration in input mode. each bit is set and cleared by software. input mode: 0: floating input 1: input pull-up (with or without interrupt see table 6 ) 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 70 o7 o6 o5 o4 o3 o2 o1 o0 st72c171 35/152 i/o ports (contd) table 7. i/o port register map and reset values address (hex.) register label 76543210 0000h padr reset value d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 0001h paddr reset value d7 0 d6 0 d5 0 dd4 0 dd3 0 dd2 0 dd1 0 dd0 0 0002h paor reset value d7 0 d6 0 d5 0 o4 0 o3 0 o2 0 o1 0 o0 0 0004h pbdr reset value d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 0005h pbddr reset value dd7 0 dd6 0 dd5 0 dd4 0 dd3 0 dd2 0 dd1 0 dd0 0 0006h pbor reset value o7 0 o6 0 o5 0 o4 0 o3 0 o2 0 o1 0 o0 0 0008h pcdr reset value d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 0009h pcddr reset value dd7 0 dd6 0 dd5 0 dd4 0 dd3 0 dd2 0 dd1 0 dd0 0 000ah pcor reset value o7 0 o6 0 o5 0 o4 0 o3 0 o2 0 o1 0 o0 0 st72c171 36/152 7.2 miscellaneous registers 7.2.1 miscellaneous register 1 (miscr1) miscellaneous register 1 is used select slow op- erating mode. bits 3, 4, 6, and 7 determine the po- larity of external interrupt requests. register address: 0020h read/write reset value: 0000 0000 (00h) bit 7:6 = pei[3:2] polarity options of external in- terrupt ei1. (port b) . these bits are set and cleared by software. these bits determine which event causes the external in- terrupt (ei1) on port b according to table 8 . table 8. ei1 ext. int. polarity options bit 5 = mco main clock out selection this bit enables the mco alternate function on the i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f osc /2 on i/o port) this bit is set and cleared by software. when set it can be used to output the internal clock to the ded- icated i/o port. bit 4:3 = pei[1:0] polarity options of external in- terrupt ei0. (port a) these bits determine which event causes the ex- ternal interrupt (ei0) on port a according to table 9 . table 9. ei0 ext. int. polarity options bit 2:1 = cp[1:0] cpu clock prescaler these bits are set and cleared by software. they determine the cpu clock when the sms bit is set according to the following table. table 10. f cpu value in slow mode bit 0 = sms slow mode select this bit is set and cleared by software. 0: normal mode - f cpu = f osc / 2 1: slow mode - the f cpu value is determined by the pc[1:0] bits. 70 pei3 pei2 mco pei1 pei0 cp1 cp0 sms mode pei3 pei2 falling edge and low level (reset state) 00 rising edge only 0 1 falling edge only 1 0 rising and falling edge 1 1 mode pei1 pei0 falling edge and low level (reset state) 00 rising edge only 0 1 falling edge only 1 0 rising and falling edge 1 1 f cpu value cp1 cp0 f osc / 4 0 0 f osc / 8 1 0 f osc / 16 0 1 f osc / 32 1 1 st72c171 37/152 7.2.2 miscellaneous register 2 (miscr2) miscellaneous register 2 is used to configure of spi and the output selection of the pwms. register address: 0040h read/write reset value: 0000 0000 (00h) bit 7:5 = not used bit 4 = spiod spi output disable this bit is used to disable the spi output on the i/o port (in both master or slave mode). 0: spi output enabled 1: spi output disabled (i/o pin free for general-purpose i/o) bit 3 = p1os pwm1 output select this bit is used to select the output for the pwm1 channel of the art/pwm timer. 0: pwm1 output on pwm1 pin 1: pwm1 output on pwm1r pin and connected to the oa2pin pin note: in order to use the pc1 port pin as a pwm output pin, bit 1 of port c must be programmed as floating input. this should be done prior to setting the p1os bit. bit 2 = p0os pwm0 output select this bit is used to select the output for the pwm0 channel of art/pwm timer. 0: pwm0 output on pwm0 pin 1: pwm0 output on pwm0r pin and connected to the oa1pin pin note: in order to use the pc2 port pin as a pwm output pin, bit 2 of port c must be programmed as floating input. this should be done prior to setting the p0os bit. bit 1 = ssm ss mode selection it is set and cleared by software. 0: normal mode - ss uses information coming from the ss pin of the spi. 1: i/o mode, the spi uses the information stored into bit ssi. bit 0 = ssi ss internal mode this bit replaces pin ss of the spi when bit ssm is set to 1. (see spi description). it is set and cleared by software. 70 - - - spiod p1os p0os ssm ssi st72c171 38/152 7.3 op-amp module 7.3.1 introduction the st7 op-amp module is designed to cover most types of microcontroller applications where analog signal amplifiers are used. it may be used to perform a a variety of functions such as: differential voltage amplifier, comparator/ threshold detector, adc zooming, impedance adaptor, general purpose operational amplifier. 7.3.2 main features this module includes: n 2 rail-to-rail spgas (software programmable gain amplifier), and 1 stand alone rail-to-rail op-amp that may be externally connected using i/o pins n a band gap voltage reference n a programmable eight-step reference voltage n art timer pwm outputs internally connected to spgas input 1 and 2. n spgas and op-amp outputs are internally connected to the adc inputs (channel 8, 9 & 10). n input offset compensation 7.3.3 general description the module contains two spgas (oa1 & oa2) and 1 stand alone operational amplifier (oa3) de- pending on the device package. oa1 and oa2 each have associated circuitry for input and gain selection. the third operational amplifier, oa3, without input and gain selection circuitry, is availa- ble in some devices (see device pin out descrip- tion). 7.3.3.1 inputs the non-inverting input of oa1 or oa2 may be connected to an i/o pin, to the band-gap reference voltage, to an 8-step voltage reference or to the analog ground. the eight-step voltage reference uses a resistive network in order to generate two voltages between 1/8 v dd and v dd (in 1/8 v dd steps) that can be connected to the non-inverting input of the two sp- gas. these voltages may be used as programma- ble thresholds with the corresponding spga used as a comparator or, with the spga programmed to have a gain of 2, 4 or 8, they may be used for ex- tending the adc precision (analog zooming). the 2 inverting inputs of oa1 or oa2 may be used to achieve this function. the input impedance of these inputs is around 2k. the art timer pwm resistive outputs are inter- nally connected to oa1pin and oa2pin pins. the pwm outputs are enabled by the pwmcr register and the resistive outputs are selected by miscella- neous register 2. refer to figure 28 . the inverting input of oa1 or oa2 may be con- nected to an i/o pin, to the analog ground or may be left unconnected (in this case the spga can be used as a repeater, with the output of the spga connected to this input via the resistive loopback). 7.3.3.2 outputs the spga outputs are connected either to exter- nal pins or, internally, to the adc input (channel 8 & 9). the output value, digitized by a schmitt trig- ger, may be read by the application software or may generate an interrupt. the oa3 output is connected to an adc input (channel 10). 7.3.3.3 advanced features the gain of oa1 or oa2 is programmed using an internal resistive network. the possible values are: 1, 2, 4, 8 and 16. the internal resistive loopback may also be de-activated in order to obtain the open-loop gain (comparator) or to use the op-amp with an external loopback network. input offset compensation in a special calibration mode (autozero mode), the negative input pin of oa1 or oa2 can be connect- ed internally to the positive input pin. this mode al- lows the measurement of the input offset voltage of the spga using the adc. this value may be stored in ram and subsequently used for offset correction (for adc conversions). refer to section 9.3.4. st72c171 39/152 op-amp module ( contd ) figure 27. op-amp module block diagram oa1nin oa1 r=2k 15r /16r r av cl =1, 2, 4, 8, 16, r=2k oa1v (1.2v) oa1o oa1pin to adc channel 8 ns1[2:0] bits az1 bit g1[2:0] bits vr1e, ps1[1:0] bits vr1[2:0] bits x v dda /8 oa1 interrupt oa1ie bit bit 8-step reference voltage 1 band gap reference voltage oa2nin oa2 r=2k 15r /16r r av cl =1, 2, 4, 8, 16, r=2k oa2v (1.2v) v ssa oa2o oa2pin to adc channel 9 ns2[2:0] bits az2 bit g2[2:0] bits vr2e, ps2[1:0] bits vr2[2:0] bits x v dda /8 oa2 interrupt oa2ie bit bit 8-step reference voltage 2 band gap reference voltage oa3 oa3o oa3nin to adc channel 10 oa3pin note: oa3 is not present on some package types. refer to the device pin description. v ssa art timer pwm0r output art timer pwm1r output st72c171 40/152 op-amp module ( contd ) 7.3.4 autozero mode when the following description refers to both oa1 or oa2, x stands for 1 or 2. in order to eliminate the adc errors due to the spga offset voltage, this voltage may be deter- mined, prior to the a/d conversion (at power on or periodically) and stored in ram. the stored value may be used afterwards to eliminate the errors of any a/d conversion that uses the spga (adc zooming). the measurement may be done inde- pendently for oa1 and oa2. the measurement algorithm has 3 steps: 1. the spga is in repeater mode (nsx[1:0] = 01), with the lowest gain (gx[2:0]=000), the autoze- roing switch is left open (azx = 0). the positive input of the op-amp is connected to a dc value, using the vrx reference voltage generator (psx[1:0] = 00), and the output is sent to the adc. under these conditions, the adc meas- ures the value: vo = vrx -voff of the spga output. 2. set the gain (g) according the application requirement. the azx bit is set to 1. the output voltage of the spga becomes: vo = vrx - voff - g * voff 3.voff calculated with 1) - 2) voff =( vo- vo) /g as the offset voltage of the spgas may vary with the common mode voltage value, the measure- ment must be done choosing vrx to match the ap- plication conditions. alternatively, nine measure- ments may be done with the noninverting input voltage varying between 0 and v dda in 1/8 v dd steps, in order to fully characterise the offset volt- age of the op-amp. 7.3.5 comparator mode with interrupts the 2 spgas can be configured in comparator mode (gx[2:0]=111). in this case the positive in- put can be connected to the internal reference voltage. the negative input can be used to receive the analog voltage to be compared with the volt- age connected to the positive input. by means of a schmitt trigger, the spga output is readable as a logical level in the oaxvr bit in the oairr register. these bits are read only. an interrupt request remains pending as long as the output value (oaxvr) is equal to the corre- sponding polarity bit (oaxpr) and when the inter- rupt enable bit (oaxie) is set. there is one inter- rupt vector for each spga. st72c171 41/152 op-amp module (contd) 7.3.6 dac function using art timer pwmr outputs the pwmr outputs are connected to a serial re- sistor and internally connected to the oa1pin/ oa2pin inputs. an external capacitor must be connected to the pwm0r/oa1pin and/or pwm1r/oa2pin pins (see figure 28 ) if the pwmr outputs are used. this feature allows the microcontroller to be used as a digital to analog converter and generating a dc voltage on the positive input pin, so the spgas may be used for the following functions: C a comparator C an amplifier of an external voltage connected to the negative input pin (oa1nin or oa2nin). C a repeater, to obtain the same voltage on the oa output pin as on the input pin, with increased cur- rent capability. figure 28 . connection of pwmr outputs to oa1 or oa2 for dac function 0.7k (typ) c ext r int pwm/art timer oa2 opamp module oa1 0.7k (max) c ext r int pwm1 pwm0r/oa1pin pwm1r/oa2pin misc2 register p1os p0os oe1 oe0 pwmcr register pwm0 p1os oe1 st72c171 42/152 op-amp module ( contd ) 7.3.7 low power modes note: low power modes have no effect on the spgas & the op-amp. they can be switched off to reduce the power consumption of the st7 (oaxon bits). 7.3.8 i nterrupts * the interrupt event occurs when the oaxp bit equals the oaxv bit value. note: the spga interrupt events are connected to 2 interrupt vectors (see interrupts chapter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on op-amp. spga interrupts cause the device to exit from wait mode. halt no effect on op-amp. spga interrupts cause the device to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt op-amp 1 output in comparator mode equals to oa1p bit value na* oa1ie yes yes op-amp 2 output in comparator mode equals to oa2p bit value na* oa2ie yes yes st72c171 43/152 7.3.9 register description oa1 control register (oa1cr) read/write reset value: 0000 00000 (00h) bit 7 = az1 oa1 autozero mode. this bit is set and reset by hardware. it enables autozero mode (used to measure the oa1 input offset). 0: autozero mode disabled 1: autozero mode enabled bit 6:4 = g1[2:0] gain control. these bits are set and reset by software and con- trol the oa1 gain by modifying the resistive loop- back network. the value of the gain is adjusted to the desired value (for inverting / non-inverting am- plification) corresponding to the selected positive input source - see ps1[1:0] table, gain adjust col- umn. bit 3:2 = ps1[1:0] positive input select / gain ad- just . these bits are set and reset by software and con- trol the oa1 positive input selection. bit 1:0 = ns1[1:0] negative input select. these bits are set and reset by software and con- trol the oa1 positive input selection. oa2 control register (oa2cr) read/write reset value: 0000 0000 (00h) bit 7 = az2 oa2 autozero mode. this bit is set and reset by hardware. it enables autozero mode (used to measure the oa2 input offset). 0: autozero mode disabled 1: autozero mode enabled bit 6:4 = g2[2:0] gain control. these bits are set and reset by software and con- trol the oa2 gain by modifying the resistive loop- back network. the value of the gain is adjusted to the desired value (for inverting/noninverting ampli- fication) corresponding to the selected positive in- put source - see ps2[1:0] table, gain adjust col- umn. 70 az1 g12 g11 g10 ps11 ps10 ns11 ns10 gain inv / ninv g12 g11 g10 -1 / 2 0 0 0 -2 / 3 0 0 1 -3 / 4 0 1 0 -4 / 5 0 1 1 -8 / 8 1 0 0 -16 / 16 1 0 1 comparator external loopback 111 oa1 positive input gain adj. ps11 ps10 8-step ref.voltage 1 inv 0 0 oa1pin ninv 0 1 band gap ref. voltage (1.2v) inv 1 0 oa1 negative input ns11 ns10 agnd 0 0 floating - repeater mode 0 1 oa1nin 1 x 70 az2 g22 g21 g20 ps21 ps20 ns21 ns20 gain inv / ninv g22 g21 g20 -1 / 2 0 0 0 -2 / 3 0 0 1 -3 / 4 0 1 0 -4 / 5 0 1 1 -8 / 8 1 0 0 -16 / 16 1 0 1 comparator external loopback 111 st72c171 44/152 op-amp module ( contd ) bit 3:2 = ps2[1:0] positive input select / gain ad- just. these bits are set and reset by software and con- trol the oa2 positive input selection. t bit 1:0 = ns2[1:0] negative input select. these bits are set and reset by software and con- trol the oa2 negative input selection. oa3 control register (oa3cr) read/write reset value: 0000 0000 (00h) bit 7 = oa3on oa3 on/off (low power) stand alone op-amp on/off control bit, it is set and reset by software. it reduces power consumption when reset. 0: op-amp 3 off 1: op-amp 3 on note: this bit must be kept cleared in devices without oa3 (refer to device block diagram and pin description) bit 6:0 = reserved. oa2 positive input gain adj. ps21 ps20 8-step ref.voltage 1 inv 0 0 oa2pin ninv 0 1 band gap ref. voltage (1.2v) inv 1 0 floating ninv 1 1 oa2 negative input ns21 ns20 agnd 0 0 floating -repeater mode 0 1 oa2nin 1 x 70 oa3on------- st72c171 45/152 op-amp module ( contd ) op-amp interrupt and readout regis- ter (oairr) read/write* reset value: 0000 0000 (00h) bit 7 = oa1ie oa1 interrupt enable this bit is set and reset by software. when it is set, it enables an interrupt to be generated if the oa1p bit and the oa1v bit have the same value. 0: oa1 interrupt disabled 1: oa1 interrupt enabled bit 6 = oa1p oa1 interrupt polarity select this bit is set and reset by software. it specifies the oa1 spga output level which will generate an in- terrupt if the bit oa1ie is set. 0: active low 1: active high bit 5 = oa1v oa1 output value (read only) this bit is set and reset by hardware. it contains the oa1 spga output voltage value filtered by a schmitt trigger. 0: oa1+ voltage < oa1- voltage 1: oa1+ voltage > oa1- voltage bit 4 = oa1on oa1 on/off (low power) this bit is set and reset by software. it reduces power consumption when reset. 0: op-amp 1 off 1: op-amp 1 on bit 3 = oa2ie oa2 interrupt enable this bit is set and reset by software. when it is set, it enables an interrupt to be generated if the oa2p bit and the oa2v bit have the same value. 0: oa2 interrupt disabled 1: oa2 interrupt enabled bit 2 = oa2p oa2 interrupt polarity select this bit is set and reset by software. it specifies the oa2 spga output level which will generate an in- terrupt if the bit oa2ie is set. 0: active low 1: active high bit 1- oa2v oa2 output value (read only) this bit is set and reset by hardware. it contains the oa2 spga output voltage value filtered by a schmitt trigger. 0: oa2+ voltage < oa2- voltage 1: oa2+ voltage > oa2- voltage bit 0 - oa2on oa2 on/off (low power) 0: op-amp 2 off (reducing power consumption) 1: op-amp 2 on note: if oa1on, oa2on and oa3on are 0, the entire module is disabled, giving the lowest power consumption. * oa1v and oa2v are read only. 70 oa1ie oa1p oa1v oa1on oa2ie oa2p oa2v oa2on st72c171 46/152 op-amp module ( contd ) voltage reference control register (oavrcr) read/write reset value: 0000 0000 (00h) bit 7 = vr2e : vr2 enable this bit is set and reset by software. when the ref- ererence voltage is selected (ps2[1:0] = 00 in the oa2cr register) it connects v ssa (analog ground) or reference voltage 2 (vr2) to the oa2 positive input. 0: oa2 positive input is connected to v ssa 1: oa2 positive input is connected to vr2 voltage value bit 6:4 = vr2[2:0] voltage selection for channel 2 of the 8-step reference voltage these bits are set and reset by software, they specify the reference voltage 2 (vr2) connected to the oa2 positive input when ps2[1:0] = 00 in the oa2cr register . . bit 3= vr1e vr1 enable this bit is set and reset by software. when the ref- ererence voltage is selected (ps1[1:0] = 00 in the oa1cr register) it connects v ssa (analog ground) or reference voltage 1 (vr1) to the oa1 positive input. 0: oa1 positive input is connected to v ssa 1: oa1 positive input is connected to vr1 voltage value bit 2:0 - vr1[2:0] voltage selection for channel 1 of the 8-step reference voltage these bits are set and reset by software, they specify the reference voltage 1 (vr1) connected to the oa1 positive input when ps1[1:0] = 00 in the oa1cr register . note: when both vr2e and vr1e are reset, the 8-step voltage reference cell is disabled and en- ters low power mode. 70 vr2e vr22 vr21 vr20 vr1e vr12 vr11 vr10 reference voltage 2 vr2e vr22 vr21 vr20 0 (v ssa )0 x x x v dda /81000 2 x v dda /81001 3 x v dda /81010 4 x v dda /81011 5 x v dda /81100 6 x v dda /81101 7 x v dda /81110 v dda 1111 reference voltage 1 vr1e vr12 vr11 vr10 0 (v ssa )0xxx v dda /81000 2 x v dda /81001 3 x v dda /81010 4 x v dda /81011 5 x v dda /81100 6 x v dda /81101 7 x v dda /8 1 1 1 v dda 111 st72c171 47/152 table 11. op-amp module register map and reset values address (hex.) register label 76543210 001bh oa1cr reset value az1 0 g12 0 g11 0 g10 0 ps11 0 ps10 0 ns11 0 ns10 0 001ch oa2cr reset value az2 0 g22 0 g21 0 g20 0 ps21 0 ps20 0 ns21 0 ns20 0 001dh oa3cr reset value oa3on 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 001eh oirr reset value oa1ie 0 oa1p 0 oa1v 0 oa2on 0 oa2ie 0 oa2p 0 oa2v 0 oa1on 0 001fh vrcr reset value vr2e 0 vr22 0 vr21 0 vr20 0 vr1e 0 vr12 0 vr11 0 vr10 0 st72c171 48/152 7.4 watchdog timer (wdg) 7.4.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counters contents before the t6 bit be- comes cleared. 7.4.2 main features n programmable timer (64 increments of 12288 cpu cycles) n programmable reset n reset (if watchdog activated) when the t6 bit reaches zero n optional reset on halt instruction (configurable by option byte) n hardware watchdog selectable by option byte. 7.4.3 functional description the counter value stored in the cr register (bits t6:t0), is decremented every 12,288 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t6:t0) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see table 13 . watchdog timing (fcpu = 8 mhz) ): C the wdga bit is set (watchdog enabled) C the t6 bit is set to prevent generating an imme- diate reset C the t5:t0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. figure 29. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) ? 12288 t1 t2 t3 t4 t5 st72c171 49/152 watchdog timer (contd) table 12. watchdog timing (f cpu = 8 mhz) notes: following a reset, the watchdog is disa- bled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). 7.4.4 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. refer to the device-specific option byte descrip- tion. 7.4.5 low power modes wait instruction no effect on watchdog. halt instruction if the watchdog reset on halt option is selected by option byte, a halt instruction causes an im- mediate reset generation if the watchdog is acti- vated (wdga bit is set). 7.4.5.1 using halt mode with the wdg (option) if the watchdog reset on halt option is not se- lected by option byte, the halt mode can be used when the watchdog is enabled. in this case, the halt instruction stops the oscilla- tor. when the oscillator is stopped, the wdg stops counting and is no longer able to generate a reset until the microcontroller receives an external inter- rupt or a reset. if an external interrupt is received, the wdg re- starts counting after 4096 cpu clocks. if a reset is generated, the wdg is disabled (reset state). recommendations C make sure that an external event is available to wake up the microcontroller from halt mode. C before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcon- troller. C when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as input pull-up with interrupt before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to ex- ternal interference or by an unforeseen logical condition. C for the same reason, reinitialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. C the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. C as the halt instruction clears the i bit in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before execut- ing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 7.4.6 interrupts none. 7.4.7 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled bit 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). cr register initial value wdg timeout period (ms) max ffh 98.304 min c0h 1.536 70 wdga t6 t5 t4 t3 t2 t1 t0 st72c171 50/152 watchdog timer (contd) table 13. wdg register map address (hex.) register name 765 4 3210 24 cr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 st72c171 51/152 7.5 16-bit timer 7.5.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including measuring the pulse lengths of up to two input sig- nals ( input capture ) or generating up to two output waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequen- cies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 7.5.2 main features n programmable prescaler: f cpu divided by 2, 4 or 8. n overflow status flag and maskable interrupt n external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge n output compare functions with: C 2 dedicated 16-bit registers C 2 dedicated programmable signals C 2 dedicated status flags C 1 dedicated maskable interrupt n input capture functions with: C 2 dedicated 16-bit registers C 2 dedicated active edge selection signals C 2 dedicated status flags C 1 dedicated maskable interrupt n pulse width modulation mode (pwm) n one pulse mode n 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 1 . *note: some timer pins may not be available (not bonded) in some st7 devices. refer to the device pin out description. when reading an input signal on a non-bonded pin, the value will always be 1. 7.5.3 functional description 7.5.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high & low. counter register (cr): C counter high register (chr) is the most sig- nificant byte (ms byte). C counter low register (clr) is the least sig- nificant byte (ls byte). alternate counter register (acr) C alternate counter high register (achr) is the most significant byte (ms byte). C alternate counter low register (aclr) is the least significant byte (ls byte). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register (sr). (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit tim- er). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 1 . the value in the counter register repeats every 131.072, 262.144 or 524.288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency. st72c171 52/152 16-bit timer (contd) figure 30. timer block diagram mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 0 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (status register) sr 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register note: if ic, oc and to interrupt requests have separate vectors then the last or is not present (see device interrupt vector table) (see note) st72c171 53/152 16-bit timer (contd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, out- put compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: C the tof bit of the sr register is set. C a timer interrupt is generated if: C toie bit of the cr1 register is set and C i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. note: the tof bit is not cleared by accessing the aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 7.5.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the exter- nal clock pin extclk that will trigger the free run- ning counter. the counter is synchronised with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the cpu clock frequency. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + d t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte st72c171 54/152 16-bit timer (contd) figure 31. counter timing diagram, internal clock divided by 2 figure 32. counter timing diagram, internal clock divided by 4 figure 33. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high. when it is low, the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 st72c171 55/152 16-bit timer (contd) 7.5.3.3 input capture in this section, the index, i , may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition is detected by the icap i pin (see figure 5). the ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure: to use the input capture function, select the fol- lowing in the cr2 register: C select the timer clock (cc[1:0]) (see table 1 ). C select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as a floating input). and select the following in the cr1 register: C set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin C select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as a floating input). when an input capture occurs: C the icf i bit is set. C the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 6 ). C a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. notes: 1. after reading the ic i hr register, the transfer of input capture data is inhibited and icf i will never be set until the ic i lr register is also read. 2. the ic i r register contains the free running counter value which corresponds to the most recent input capture. 3. the 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. in one pulse mode and pwm mode only the input capture 2 function can be used. 5. the alternate inputs (icap1 & icap2) are always directly connected to the timer. so any transitions on these pins activate the input cap- ture function. moreover if one of the icap i pin is configured as an input and the second one as an output, an interrupt can be generated if the user tog- gles the output pin and if the icie bit is set. this can be avoided if the input capture func- tion i is disabled by reading the ic i hr (see note 1). 6. the tof bit can be used with an interrupt in order to measure events that exceed the timer range (ffffh). ms byte ls byte icir ic i hr ic i lr st72c171 56/152 16-bit timer (contd) figure 34. input capture block diagram figure 35. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge. st72c171 57/152 16-bit timer (contd) 7.5.3.4 output compare in this section, the index, i , may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: C assigns pins with a programmable value if the ocie bit is set C sets a flag in the status register C generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: C set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. C select the timer clock (cc[1:0]) (see table 1 ). and select the following in the cr1 register: C select the olvl i bit to applied to the ocmp i pins after the match occurs. C set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: C ocf i bit is set. C the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). C a timer interrupt is generated if the ocie bit is set in the cr2 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 de- pending on cc[1:0] bits, see table 1 ) if the timer clock is an external clock, the formula is: where: d t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (i.e. clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: C write to the oc i hr register (further compares are inhibited). C read the sr register (first step of the clearance of the ocf i bit, which may be already set). C write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr d oc i r = d t * f cpu presc d oc i r = d t * f ext st72c171 58/152 16-bit timer (contd) notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. when the timer clock is f cpu /2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 8 ). this behaviour is the same in opm or pwm mode. when the timer clock is f cpu /4, f cpu /8 or in external clock mode, ocf i and ocmp i are set while the counter value equals the oc i r regis- ter value plus 1 (see figure 9 ). 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. folvl i bits have no effect in either one-pulse mode or pwm mode. figure 36. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 st72c171 59/152 16-bit timer (contd) figure 37. output compare timing diagram, f timer =f cpu /2 figure 38. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i ) st72c171 60/152 16-bit timer (contd) 7.5.3.5 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. select the following in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. C select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: C set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. C set the opm bit. C select the timer clock cc[1:0] (see table 1 ). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and the olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the value fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specific timing application can be calculated using the fol- lowing formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on the cc[1:0] bits, see table 1 ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin (see figure 10 ). notes: 1. the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. 4. the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5. when one pulse mode is used oc1r is dedi- cated to this mode. nevertheless oc2r and ocf2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the olvl2 level is dedi- cated to one pulse mode. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 st72c171 61/152 16-bit timer (contd) figure 39. one pulse mode timing example figure 40. pulse width modulation mode timing example counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1 fffc fffd fffe 2ed0 2ed1 2ed2 st72c171 62/152 16-bit timer (contd) 7.5.3.6 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. the pulse width modulation mode uses the com- plete output compare 1 function plus the oc2r register, and so these functions cannot be used when the pwm mode is activated. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corre- sponding to the period of the pulse if olvl1=0 and olvl2=1, using the formula in the oppo- site column. 3. select the following in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc1r register. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: C set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. C set the pwm bit. C select the timer clock (cc[1:0]) (see table 1 ). if olvl1=1 and olvl2=0, the length of the posi- tive pulse is the difference between the oc2r and oc1r registers. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on cc[1:0] bits, see table 1 ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 11 ) notes: 1. after a write instruction to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. 2. the ocf1 and ocf2 bits cannot be set by hardware in pwm mode, therefore the output compare interrupt is inhibited. 3. the icf1 bit is set by hardware when the coun- ter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4. in pwm mode the icap1 pin can not be used to perform input capture because it is discon- nected from the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset after each period and icf1 can also generate an interrupt if icie is set. 5. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 st72c171 63/152 16-bit timer (contd) 7.5.4 low power modes 7.5.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 7.5.6 summary of timer modes 1) see note 4 in section 0.1.3.5 one pulse mode 2) see note 5 in section 0.1.3.5 one pulse mode 3) see note 4 in section 0.1.3.6 pulse width modulation mode mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with exit from halt mode capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequent- ly, when the mcu is woken up by an interrupt with exit from halt mode capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie yes no input capture 2 event icf2 yes no output compare 1 event (not available in pwm mode) ocf1 ocie yes no output compare 2 event (not available in pwm mode) ocf2 yes no timer overflow event tof toie yes no modes available resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2) yes yes yes yes one pulse mode no not recommended 1) no partially 2) pwm mode no not recommended 3) no no st72c171 64/152 16-bit timer (contd) 7.5.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 st72c171 65/152 16-bit timer (contd) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the internal output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the internal output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bits 3:2 = cc[1:0] clock control. the timer clock mode depends on these bits: table 14. clock control bits note : if the external clock pin is not available, pro- gramming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin (extclk) will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 0 1 f cpu / 8 1 0 external clock (where available) 11 st72c171 66/152 16-bit timer (contd) status register (sr) read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter matches the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) register. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter has rolled over from ffffh to 0000h. to clear this bit, first read the sr register, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter matches the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) register. bit 2-0 = reserved, forced by hardware to 0. input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 icf1 ocf1 tof icf2 ocf2 0 0 0 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb st72c171 67/152 16-bit timer (contd) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb st72c171 68/152 table 15. 16-bit timer register map and reset values address (hex.) register name 76543210 0032h cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 0031h cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 0033h sr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 - 0 - 0 - 0 0034h- 0035h ic1hr reset value msb - ------ lsb - ic1lr reset value msb - ------ lsb - 0036h- 0037h oc1hr reset value msb 1 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 oc1lr reset value msb 0 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 003eh- 003fh oc2hr reset value msb 1 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 oc2lr reset value msb 0 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 0038h- 0039h chr reset value msb 1111111 lsb 1 clr reset value msb 1111110 lsb 0 003ah- 003bh achr reset value msb 1111111 lsb 1 aclr reset value msb 1111110 lsb 0 003ch- 003dh ic2hr reset value msb - ------ lsb - ic2lr reset value msb - ------ lsb - st72c171 69/152 7.6 pwm auto-reload timer (art) 7.6.1 introduction the pulse width modulated auto-reload timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. these resources allow five possible operating modes: C generation of up to 4 independent pwm signals C output compare and time base interrupt C up to two input capture functions C external event detector C up to two external interrupt sources the three first modes can be used together with a single counter frequency. the timer can be used to wake up the mcu from wait and halt modes. figure 41. pwm auto-reload timer block diagram ovf interrupt excl cc2 cc1 cc0 tce fcrl oie ovf artcsr f input pwmx port function alternate ocrx compare register programmable prescaler 8-bit counter (car register) arr register icrx register load opx polarity control oex pwmcr mux f cpu dcrx register load f counter artclk f ext articx icfx icsx iccsr load icx interrupt iciex input capture control st72c171 70/152 pwm auto-reload timer (contd) 7.6.2 functional description counter the free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal. it is possible to read or write the contents of the counter on the fly by reading or writing the counter access register (car). when a counter overflow occurs, the counter is automatically reloaded with the contents of the arr register (the prescaler is not affected). counter clock and prescaler the counter clock frequency is given by: f counter = f input / 2 cc[2:0] the timer counters input clock (f input ) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by cc[2:0] bits in the control/status register (csr). thus the division factor of the prescaler can be set to 2 n (where n = 0, 1,..7). this f input frequency source is selected through the excl bit of the csr register and can be either the f cpu or an external input frequency f ext . the clock input to the counter is enabled by the tce (timer counter enable) bit in the csr regis- ter. when tce is reset, the counter is stopped and the prescaler and counter contents are frozen. when tce is set, the counter runs at the rate of the selected clock source. counter and prescaler initialization after reset, the counter and the prescaler are cleared and f input = f cpu . the counter can be initialized by: C writing to the arr register and then setting the fcrl (force counter re-load) and the tce (timer counter enable) bits in the csr register. C writing to the car counter access register, in both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known value. direct access to the prescaler is not possible. output compare control the timer compare function is based on four differ- ent comparisons with the counter (one for each pwmx output). each comparison is made be- tween the counter value and an output compare register (ocrx) value. this ocrx register can not be accessed directly, it is loaded from the duty cy- cle register (dcrx) at each overflow of the coun- ter. this double buffering method avoids glitch gener- ation when changing the duty cycle on the fly. figure 42. output compare control counter fdh feh ffh fdh feh ffh fdh feh arr=fdh f counter ocrx dcrx fdh feh fdh feh ffh pwmx st72c171 71/152 pwm auto-reload timer (contd) independent pwm signal generation this mode allows up to four pulse width modulat- ed signals to be generated on the pwmx output pins with minimum core processing overhead. this function is stopped during halt mode. each pwmx output signal can be selected inde- pendently using the corresponding oex bit in the pwm control register (pwmcr). when this bit is set, the corresponding i/o pin is configured as out- put push-pull alternate function. the pwm signals all have the same frequency which is controlled by the counter period and the arr register value. f pwm = f counter / (256 - arr) when a counter overflow occurs, the pwmx pin level is changed depending on the corresponding opx (output polarity) bit in the pwmcr register. when the counter reaches the value contained in one of the output compare register (ocrx) the corresponding pwmx pin level is restored. it should be noted that the reload values will also affect the value and the resolution of the duty cycle of the pwm output signal. to obtain a signal on a pwmx pin, the contents of the ocrx register must be greater than the contents of the arr register. the maximum available resolution for the pwmx duty cycle is: resolution = 1 / (256 - arr) note : to get the maximum resolution (1/256), the arr register must be 0. with this maximum reso- lution, 0% and 100% can be obtained by changing the polarity. figure 43. pwm auto-reload timer function figure 44. pwm signal from 0% to 100% duty cycle duty cycle register auto-reload register pwmx output t 255 000 with oex=1 and opx=0 (arr) (dcrx) with oex=1 and opx=1 counter counter pwmx output t with oex=1 and opx=0 fdh feh ffh fdh feh ffh fdh feh ocrx=fch ocrx=fdh ocrx=feh ocrx=ffh arr=fdh f counter st72c171 72/152 pwm auto-reload timer (contd) output compare and time base interrupt on overflow, the ovf flag of the csr register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, oie, in the csr register, is set. the ovf flag must be reset by the user software. this interrupt can be used as a time base in the application. external clock and event detector mode using the f ext external prescaler input clock, the auto-reload timer can be used as an external clock event detector. in this mode, the arr register is used to select the n event number of events to be counted before setting the ovf flag. n event = 256 - arr when entering halt mode while f ext is selected, all the timer control registers are frozen but the counter continues to increment. if the oie bit is set, the next overflow of the counter will generate an interrupt which wakes up the mcu. figure 45. external event detector example (3 counts) counter t fdh feh ffh fdh ovf csr read interrupt arr=fdh f ext =f counter feh ffh fdh if oie=1 interrupt if oie=1 csr read st72c171 73/152 pwm auto-reload timer (contd) input capture function this mode allows the measurement of external signal pulse widths through icrx registers. each input capture can generate an interrupt inde- pendently on a selected input signal transition. this event is flagged by a set of the corresponding cfx bits of the input capture control/status regis- ter (iccsr). these input capture interrupts are enabled through the ciex bits of the iccsr register. the active transition (falling or rising edge) is soft- ware programmable through the csx bits of the iccsr register. the read only input capture registers (icrx) are used to latch the auto-reload counter value when a transition is detected on the articx pin (cfx bit set in iccsr register). after fetching the interrupt vector, the cfx flags can be read to identify the in- terrupt source. note : after a capture detection, data transfer in the icrx register is inhibited until it is read (clear- ing the cfx bit). the timer interrupt remains pending while the cfx flag is set when the interrupt is enabled (ciex bit set). this means, the icrx register has to be read at each capture event to clear the cfx flag. the timing resolution is given by auto-reload coun- ter cycle time (1/f counter ). note: during halt mode, if both input capture and external clock are enabled, the icrx register value is not guaranteed if the input capture pin and the external clock change simultaneously. external interrupt capability this mode allows the input capture capabilities to be used as external interrupt sources. the inter- rupts are generated on the edge of the articx signal. the edge sensitivity of the external interrupts is programmable (csx bit of iccsr register) and they are independently enabled through ciex bits of the iccsr register. after fetching the interrupt vector, the cfx flags can be read to identify the in- terrupt source. during halt mode, the external interrupts can be used to wake up the micro (if the ciex bit is set). figure 46. input capture timing diagram 04h counter t 01h f counter xxh 02h 03h 05h 06h 07h 04h articx pin cfx flag icrx register interrupt st72c171 74/152 pwm auto-reload timer (contd) 7.6.3 register description control / status register (csr) read/write reset value: 0000 0000 (00h) bit 7 = excl external clock this bit is set and cleared by software. it selects the input clock for the 7-bit prescaler. 0: cpu clock. 1: external clock. bit 6:4 = cc[2:0] counter clock control these bits are set and cleared by software. they determine the prescaler division ratio from f input . bit 3 = tce timer counter enable this bit is set and cleared by software. it puts the timer in the lowest power consumption mode. 0: counter stopped (prescaler and counter frozen). 1: counter running. bit 2 = fcrl force counter re-load this bit is write-only and any attempt to read it will yield a logical zero. when set, it causes the contents of arr register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. bit 1 = oie overflow interrupt enable this bit is set and cleared by software. it allows to enable/disable the interrupt which is generated when the ovf bit is set. 0: overflow interrupt disable. 1: overflow interrupt enable. bit 0 = ovf overflow flag this bit is set by hardware and cleared by software reading the csr register. it indicates the transition of the counter from ffh to the arr value . 0: new transition not yet reached 1: transition reached counter access register (car) read/write reset value: 0000 0000 (00h) bit 7:0 = ca[7:0] counter access data these bits can be set and cleared either by hard- ware or by software. the car register is used to read or write the auto-reload counter on the fly (while it is counting). auto-reload register (arr) read/write reset value: 0000 0000 (00h) bit 7:0 = ar[7:0] counter auto-reload data these bits are set and cleared by software. they are used to hold the auto-reload value which is au- tomatically loaded in the counter when an overflow occurs. at the same time, the pwm output levels are changed according to the corresponding opx bit in the pwmcr register. this register has two pwm management func- tions: C adjusting the pwm frequency C setting the pwm duty cycle resolution pwm frequency vs. resolution: 70 excl cc2 cc1 cc0 tce fcrl oie ovf f counter with f input =8 mhz cc2 cc1 cc0 f input f input / 2 f input / 4 f input / 8 f input / 16 f input / 32 f input / 64 f input / 128 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 250 khz 125 khz 62.5 khz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 70 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 70 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 arr value resolution f pwm min max 0 8-bit ~0.244-khz 31.25-khz [ 0..127 ] > 7-bit ~0.244-khz 62.5-khz [ 128..191 ] > 6-bit ~0.488-khz 125-khz [ 192..223 ] > 5-bit ~0.977-khz 250-khz [ 224..239 ] > 4-bit ~1.953-khz 500-khz st72c171 75/152 pwm auto-reload timer (contd) pwm control register (pwmcr) read/write reset value: 0000 0000 (00h) bit 7:6 = reserved. bit 5:4 = oe[1:0] pwm output enable these bits are set and cleared by software. they enable or disable the pwm output channels inde- pendently acting on the corresponding i/o pin. 0: pwm output disabled. 1: pwm output enabled. bit 3:2 = reserved. bit 1:0 = op[1:0] pwm output polarity these bits are set and cleared by software. they independently select the polarity of the two pwm output signals. note : when an opx bit is modified, the pwmx out- put signal polarity is immediately reversed. duty cycle registers (dcrx) read/write reset value: 0000 0000 (00h) bit 7:0 = dc[7:0] duty cycle data these bits are set and cleared by software. a dcrx register is associated with the ocrx reg- ister of each pwm channel to determine the sec- ond edge location of the pwm signal (the first edge location is common to all channels and given by the arr register). these dcr registers allow the duty cycle to be set independently for each pwm channel. 70 00oe1oe000op1op0 pwmx output level opx counter <= ocrx counter > ocrx 100 011 70 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 st72c171 76/152 pwm auto-reload timer (contd) input capture control / status register (iccsr) read/write reset value: 0000 0000 (00h) bit 7:6 = reserved, always read as 0. bit 5:4 = cs[2:1] capture sensitivity these bits are set and cleared by software. they determine the trigger event polarity on the corre- sponding input capture channel. 0: falling edge triggers capture on channel x. 1: rising edge triggers capture on channel x. bit 3:2 = cie[2:1] capture interrupt enable these bits are set and cleared by software. they allow to enable or not the input capture channel in- terrupts independently. 0: input capture channel x interrupt disabled. 1: input capture channel x interrupt enabled. bit 1:0 = cf[2:1] capture flag these bits are set by hardware and cleared by software reading the corresponding icrx register. each cfx bit indicates that an input capture x has occurred. 0: no input capture on channel x. 1: an input capture has occured on channel x. input capture registers (icrx) read only reset value: 0000 0000 (00h) bit 7:0 = ic[7:0] input capture data these read only bits are set and cleared by hard- ware. an icrx register contains the 8-bit auto-re- load counter value transferred by the input capture channel x event. 70 0 0 cs2 cs1 cie2 cie1 cf2 cf1 70 ic7 ic6 ic5 ic4 ic3 ic2 ic1 ic0 st72c171 77/152 pwm auto-reload timer (contd) table 16. pwm auto-reload timer register map and reset values address (hex.) register label 76543210 0074h pwmdcr1 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0075h pwmdcr0 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0076h pwmcr reset value 0 0 0 0 oe1 0 oe0 0 0 0 0 0 op1 0 op0 0 0077h artcsr reset value excl 0 cc2 0 cc1 0 cc0 0 tce 0 fcrl 0 rie 0 ovf 0 0078h artcar reset value ca7 0 ca6 0 ca5 0 ca4 0 ca3 0 ca2 0 ca1 0 ca0 0 0079h artarr reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0 007ah articcsr reset value 00 ce2 0 ce1 0 cs2 0 cs1 0 cf2 0 cf1 0 007bh articr1 reset value ic7 0 ic6 0 ic5 0 ic4 0 ic3 0 ic2 0 ic1 0 ic0 0 st72c171 78/152 7.7 serial communications interface (sci) 7.7.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. 7.7.2 main features n full duplex, asynchronous communications n nrz standard format (mark/space) n independently programmable transmit and receive baud rates up to 250k baud. n programmable data word length (8 or 9 bits) n receive buffer full, transmit buffer empty and end of transmission flags n two receiver wake-up modes: C address bit (msb) C idle line n muting function for multiprocessor configurations n separate enable bits for transmitter and receiver n three error detection flags: C overrun error C noise error C frame error n five interrupt sources with flags: C transmit data register empty C transmission complete C receive data register full C idle line received C overrun error detected 7.7.3 general description the interface is externally connected to another device by two pins (see figure 47 ): C tdo: transmit data output. when the transmit- ter is disabled, the output pin returns to its i/o port configuration. when the transmitter is ena- bled and nothing is to be transmitted, the tdo pin is at high level. C rdi: receive data input is the serial data input. oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. through this pins, serial data is transmitted and re- ceived as frames comprising: C an idle line prior to transmission or reception C a start bit C a data word (8 or 9 bits) least significant bit first C a stop bit indicating that the frame is complete. st72c171 79/152 serial communications interface (contd) figure 47. sci block diagram wake up unit receiver control sr transmit control tdre tc rdrf idle or nf fe - cr2 sbk rwu re te ilie rie tcie tie sci control interrupt cr1 r8 t8 - m wake - -- received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) dr transmitter clock receiver clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /2 /pr /16 baud rate generator st72c171 80/152 serial communications interface (contd) 7.7.4 functional description the block diagram of the serial control interface, is shown in figure 47 . it contains 4 dedicated reg- isters: C two control registers (cr1 & cr2) C a status register (sr) C a baud rate register (brr) refer to the register descriptions in section 9.7.7 for the definitions of each bit. 7.7.4.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the cr1 register (see figure 47 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of 1s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving 0s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an ex- tra 1 bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 48. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra 1 data frame break frame start bit extra 1 data frame next data frame next data frame st72c171 81/152 serial communications interface (contd) 7.7.4.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the cr1 reg- ister. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the dr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 47 ). procedure C select the m bit to define the word length. C select the desired baud rate using the brr reg- ister. C set the te bit to assign the tdo pin to the alter- nate function and to send a idle frame as first transmission. C access the sr register and write the data to send in the dr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. the following software sequence is always to clear the tdre bit: 1. an access to the sr register 2. a write to the dr register the tdre bit is set by hardware and it indicates that: C the tdr register is empty. C the data transfer is beginning. C the next data can be written in the dr register without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the cc register. when a transmission is taking place, a write in- struction to the dr register stores the data in the tdr register which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write in- struction to the dr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the cc register. the following software sequence is always to clear the tc bit: 1. an access to the sr register 2. a write to the dr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit l oads the shift register with a break character. the break frame length depends on the m bit (see figure 48 ). as long as the sbk bit is set, the sci sends break frames to the tdo pin. after clearing this bit by software, the sci inserts a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a trans- mission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set, i.e. before writing the next byte in the dr. st72c171 82/152 serial communications interface (contd) 7.7.4.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the cr1 reg- ister. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, the dr register consists of a buffer (rdr) between the internal bus and the received shift register (see figure 47 ). procedure C select the m bit to define the word length. C select the desired baud rate using the brr reg- ister. C set the re bit to enable the receiverto begin searching for a start bit. when a character is received: C the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. C an interrupt is generated if the rie bit is set and the i bit is cleared in the cc register. C the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the sr register 2. a read to the dr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci han- dles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ilie bit is set and the i bit is cleared in the cc register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the tdr register as long as the rdrf bit is not cleared. when a overrun error occurs: C the or bit is set. C the rdr content will not be lost. C the shift register will be overwritten. C an interrupt is generated if the rie bit is set and the i bit is cleared in the cc register. the or bit is reset by an access to the sr register followed by a dr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. when noise is detected in a frame: C the nf is set at the rising edge of the rdrf bit. C data is transferred from the shift register to the dr register. C no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf bit is reset by a sr register read operation followed by a dr register read operation. framing error a framing error is detected when: C the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. C a break is received. when the framing error is detected: C the fe bit is set by hardware C data is transferred from the shift register to the dr register. C no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a sr register read operation followed by a dr register read operation. st72c171 83/152 serial communications interface (contd) 7.7.4.4 baud rate generation the baud rates for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp0 & scp1 bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct0, sct1 & sct2 bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr0,scr1 & scr2 bits) all these bits are in the brr register. example: if f cpu is 8 mhz and if pr=13 and tr=rr=1, the transmit and receive baud rates are 19200 bauds. note: the baud rate registers must not be changed while the transmitter or the receiver is en- abled. 7.7.4.5 receiver muting and wake-up feature in multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interrupt are inhibited. a muted receiver may be awakened by one of the following two ways: C by idle line detection if the wake bit is reset, C by address mark detection if the wake bit is set. the receiver wakes-up by idle line detection when the receive line has recognised an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. the receiver wakes-up by address mark detec- tion when it received a 1 as the most significant bit of a word, thus indicating that the message is an address. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to re- ceive this word normally and to use it as an ad- dress word. tx = (32 * pr) * tr f cpu rx = (32 * pr) * rr f cpu st72c171 84/152 serial communications interface (contd) 7.7.5 low power modes 7.7.6 interrupts the sci interrupt events are connected to the same interrupt vector (see interrupts chapter). these events generate an interrupt if the corre- sponding enable control bit is set and the inter- rupt mask in the cc register is reset (rim instruc- tion). mode description wait no effect on sci. sci interrupts exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitting/receiving until halt mode is exited. interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission complete tc tcie yes no received data ready to be read rdrf rie yes no overrrun error detected or yes no idle line detected idle ilie yes no st72c171 85/152 serial communications interface (contd) 7.7.7 register description status register (sr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if tie =1 in the cr2 register. it is cleared by a software sequence (an access to the sr register followed by a write to the dr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note : data will not be transferred to the shift regis- ter as long as the tdre bit is not reset. bit 6 = tc transmission complete. this bit is set by hardware when transmission of a frame containing data, a preamble or a break is complete. an interrupt is generated if tcie=1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a write to the dr register). 0: transmission is not complete 1: transmission is complete bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred into the dr register. an interrupt is generated if rie=1 in the cr2 register. it is cleared by hardware when re=0 or by a software sequence (an access to the sr register followed by a read to the dr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when an idle line is de- tected. an interrupt is generated if ilie=1 in the cr2 register. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc- curs). this bit is not set by an idle line when the re- ceiver wakes up from wake-up mode. bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf=1. an interrupt is generated if rie=1 in the cr2 reg- ister. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no overrun error 1: overrun error is detected note: when this bit is set the rdr register content will not be lost but the shift register will be overwrit- ten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr regis- ter). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be transferred and only the or bit will be set. bit 0 = reserved, forced by hardware to 0. 70 tdre tc rdrf idle or nf fe 0 st72c171 86/152 serial communications interface (contd) control register 1 (cr1) read/write reset value: undefined bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m=1. bit 5 = reserved, forced by hardware to 0. bit 4 = m word length. this bit determines the data length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark bit 2:0 = reserved, forced by hardware to 0. control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre=1 in the sr register. bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the sr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the sr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the sr register. bit 3 = te transmitter enable. this bit enables the transmitter and assigns the tdo pin to the alternate function. it is set and cleared by software. 0: transmitter is disabled, the tdo pin is back to the i/o port configuration. 1: transmitter is enabled note: during transmission, a 0 pulse on the te bit (0 followed by 1) sends a preamble after the current word. bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled, it resets the rdrf, idle, or, nf and fe bits of the sr register. 1: receiver is enabled and begins searching for a start bit. bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to 1 and then to 0, the transmitter will send a br eak word at the end of the current word. 70 r8 t8 0 m wake 0 0 0 70 tie tcie rie ilie te re rwu sbk st72c171 87/152 serial communications interface (contd) data register (dr) read/write reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 47 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 47 ). baud rate register (brr) read/write reset value: 00xx xxxx (xxh) bit 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bit 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits, define the total division applied to the bus clock to yield the transmit rate clock in convention- al baud rate generator mode. bit 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp1 & scp0 bits, define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividing factor sct2 sct1 sct0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1 rr dividing factor scr2 scr1 scr0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1 st72c171 88/152 table 17. sci register map and reset values address (hex.) register name 76543210 0050h sr reset value d7 - d6 - d5 - d4 - d3 - d2 - d1 - d0 - 0051h dr reset value spie 0 spe 0 - 0 mstr 0 cpol x cpha x spr1 x spr0 x 0052h brr reset value spif 0 wcol 0 - 0 modf 0 - 0 - 0 - 0 - 0 0053h cr1 reset value d7 - d6 - d5 - d4 - d3 - d2 - d1 - d0 - 0054h cr2 reset value spie 0 spe 0 - 0 mstr 0 cpol x cpha x spr1 x spr0 x st72c171 89/152 7.8 serial peripheral interface (spi) 7.8.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. the spi is normally used for communication be- tween the microcontroller and external peripherals or another microcontroller. refer to the pin description chapter for the device- specific pin-out. 7.8.2 main features n full duplex, three-wire synchronous transfers n master or slave operation n four master mode frequencies n maximum slave mode frequency = fcpu/2. n four programmable master bit rates n programmable clock polarity and phase n end of transfer interrupt flag n write collision flag protection n master mode fault protection capability. 7.8.3 general description the spi is connected to external devices through 4 alternate pins: C miso: master in slave out pin C mosi: master out slave in pin C sck: serial clock pin Css : slave select pin a basic example of interconnections between a single master and a single slave is illustrated on figure 49 . the mosi pins are connected together as are miso pins. in this way data is transferred serially between master and slave (most significant bit first). when the master device transmits data to a slave device via mosi pin, the slave device responds by sending data to the master device via the miso pin. this implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master de- vice via the sck pin). thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. a status flag is used to indicate that the i/o operation is com- plete. four possible data/clock timing relationships may be chosen (see figure 52 ) but master and slave must be programmed with the same timing mode. figure 49. serial peripheral interface master/slave 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit st72c171 90/152 serial peripheral interface (contd) figure 50. serial peripheral interface block diagram dr read buffer 8-bit shift register write read internal bus spi spie spe spr2 mstr cpha spr0 spr1 cpol spif wcol modf serial clock generator mosi miso ss sck control state cr sr - -- -- it request master control st72c171 91/152 serial peripheral interface (contd) 7.8.4 functional description figure 49 shows the serial peripheral interface (spi) block diagram. this interface contains 3 dedicated registers: C a control register (cr) C a status register (sr) C a data register (dr) refer to the cr, sr and dr registers in section 9.8.7 for the bit definitions. 7.8.4.1 master configuration in a master configuration, the serial clock is gener- ated on the sck pin. procedure C select the spr0 & spr1 bits to define the se- rial clock baud rate (see cr register). C select the cpol and cpha bits to define one of the four relationships between the data transfer and the serial clock (see figure 52 ). Cthe ss pin must be connected to a high level signal during the complete byte transmit se- quence. C the mstr and spe bits must be set (they re- main set only if the ss pin is connected to a high level signal). in this configuration the mosi pin is a data output and to the miso pin is a data input. transmit sequence the transmit sequence begins when a byte is writ- ten the dr register. the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: C the spif bit is set by hardware C an interrupt is generated if the spie bit is set and the i bit in the ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set 2. a read to the dr register. note: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read. st72c171 92/152 serial peripheral interface (contd) 7.8.4.2 slave configuration in slave configuration, the serial clock is received on the sck pin from the master device. the value of the spr0 & spr1 bits is not used for the data transfer. procedure C for correct data transfer, the slave device must be in the same timing mode as the mas- ter device (cpol and cpha bits). see figure 52 . Cthe ss pin must be connected to a low level signal during the complete byte transmit se- quence. C clear the mstr bit and set the spe bit to as- sign the pins to alternate function. in this configuration the mosi pin is a data input and the miso pin is a data output. transmit sequence the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: C the spif bit is set by hardware C an interrupt is generated if spie bit is set and i bit in ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set. 2.a read to the dr register. notes: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 9.8.4.6 ). depending on the cpha bit, the ss pin has to be set to write to the dr register between each data byte transfer to avoid a write collision (see section 9.8.4.4 ). st72c171 93/152 serial peripheral interface (contd) 7.8.4.3 data transfer format during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). the serial clock is used to syn- chronize the data transfer during a sequence of eight clock pulses. the ss pin allows individual selection of a slave device; the other slave devices that are not select- ed do not interfere with the spi transfer. clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits. the cpol (clock polarity) bit controls the steady state value of the clock when no data is being transferred. this bit affects both master and slave modes. the combination between the cpol and cpha (clock phase) bits selects the data capture clock edge. figure 52 , shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. the ss pin is the slave device select input and can be driven by the master device. the master device applies data to its mosi pin- clock edge before the capture clock edge. cpha bit is set the second edge on the sck pin (falling edge if the cpol bit is reset, rising edge if the cpol bit is set) is the msbit capture strobe. data is latched on the occurrence of the second clock transition. no write collision should occur even if the ss pin stays low during a transfer of several bytes (see figure 51 ). cpha bit is reset the first edge on the sck pin (falling edge if cpol bit is set, rising edge if cpol bit is reset) is the msbit capture strobe. data is latched on the oc- currence of the first clock transition. the ss pin must be toggled high and low between each byte transmitted (see figure 51 ). to protect the transmission from a write collision a low value on the ss pin of a slave device freezes the data in its dr register and does not allow it to be altered. therefore the ss pin must be high to write a new data byte in the dr without producing a write collision. figure 51. cpha / ss timing diagram mosi/miso master ss slave ss (cpha=0) slave ss (cpha=1) byte 1 byte 2 byte 3 vr02131a st72c171 94/152 serial peripheral interface (contd) figure 52. data clock timing diagram cpol = 1) cpol = 0) miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) vr02131b msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit sclk (with sclk (with st72c171 95/152 serial peripheral interface (contd) 7.8.4.4 write collision error a write collision occurs when the software tries to write to the dr register while a data transfer is tak- ing place with an external device. when this hap- pens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. in slave mode when the cpha bit is set: the slave device will receive a clock (sck) edge prior to the latch of the first data transfer. this first clock edge will freeze the data in the slave device dr register and output the msbit on to the exter- nal miso pin of the slave device. the ss pin low state enables the slave device but the output of the msbit onto the miso pin does not take place until the first data transfer clock edge. when the cpha bit is reset: data is latched on the occurrence of the first clock transition. the slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the dr register after its ss pin has been pulled low. for this reason, the ss pin must be high, between each data byte transfer, to allow the cpu to write in the dr register without generating a write colli- sion. in master mode collision in the master device is defined as a write of the dr register while the internal serial clock (sck) is in the process of transfer. the ss pin signal must be always high on the master device. wcol bit the wcol bit in the sr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 53 ). figure 53. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read sr read dr write dr 2nd step spif =0 wcol=0 spif =0 wcol=0 if no transfer has started wcol=1 if a transfer has started clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 before the 2nd step read sr read dr note: writing in dr register in- stead of reading in it do not reset wcol bit read sr or then then then st72c171 96/152 serial peripheral interface (contd) 7.8.4.5 master mode fault master mode fault occurs when the master device has its ss pin pulled low, then the modf bit is set. master mode fault affects the spi peripheral in the following ways: C the modf bit is set and an spi interrupt is generated if the spie bit is set. C the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. C the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read or write access to the sr register while the modf bit is set. 2. a write to the cr register. notes: to avoid any multiple slave conflicts in the case of a system comprising several mcus, the ss pin must be pulled high during the clearing se- quence of the modf bit. the spe and mstr bits may be restored to their original state during or af- ter this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device the modf bit can not be set, but in a multi master configuration the device can be in slave mode with this modf bit set. the modf bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine. 7.8.4.6 overrun condition an overrun condition occurs when the master de- vice has sent several data bytes and the slave de- vice has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the dr register returns this byte. all other bytes are lost. this condition is not detected by the spi peripher- al. st72c171 97/152 serial peripheral interface (contd) 7.8.4.7 single master and multimaster configurations there are two types of spi systems: C single master system C multimaster system single master system a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 54 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written its dr regis- ter. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the cr register and the modf bit in the sr register. figure 54. single master configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu st72c171 98/152 serial peripheral interface (contd) 7.8.5 low power modes 7.8.6 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the mcu is woken up by an interrupt with exit from halt mode capability. interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes no master mode fault event modf yes no st72c171 99/152 serial peripheral interface (contd) 7.8.7 register description control register (cr) read/write reset value: 0000xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1 or modf=1 in the sr register bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 9.8.4.5 master mode fault ). 0: i/o port connected to pins 1: spi alternate functions connected to pins the spe bit is cleared by reset, so the spi periph- eral is not initially connected to the external pins. bit 5 = spr2 divider enable . this bit is set and cleared by software and it is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 19 . 0: divider by 2 enabled 1: divider by 2 disabled bit 4 = mstr master. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 9.8.4.5 master mode fault ). 0: slave mode is selected 1: master mode is selected, the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are re- versed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the steady state of the serial clock. the cpol bit affects both the master and slave modes. 0: the steady state is a low value at the sck pin. 1: the steady state is a high value at the sck pin. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. bit 1:0 = spr[1 : 0] serial peripheral rate. these bits are set and cleared by software.used with the spr2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. these 2 bits have no effect in slave mode. table 18. serial peripheral baud rate 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1 st72c171 100/152 serial peripheral interface (contd) status register (sr) read only reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag. this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the cr register. it is cleared by a soft- ware sequence (an access to the sr register fol- lowed by a read or write to the dr register). 0: data transfer is in progress or has been ap- proved by a clearing sequence. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the dr register are inhibited. bit 6 = wcol write collision status. this bit is set by hardware when a write to the dr register is done during a transmit sequence. it is cleared by a software sequence (see figure 53 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = unused. bit 4 = modf mode fault flag. this bit is set by hardware when the ss pin is pulled low in master mode (see section 9.8.4.5 master mode fault ). an spi interrupt can be gen- erated if spie=1 in the cr register. this bit is cleared by a software sequence (an access to the sr register while modf=1 followed by a write to the cr register). 0: no master mode fault detected 1: a fault in master mode has been detected bits 3-0 = unused. data i/o register (dr) read/write reset value: undefined the dr register is used to transmit and receive data on the serial bus. in the master device only a write to this register will initiate transmission/re- ception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. warning: a write to the dr register places data directly into the shift register for transmission. a write to the the dr register returns the value lo- cated in the buffer and not the contents of the shift register (see figure 50 ). 70 spifwcol-modf---- 70 d7 d6 d5 d4 d3 d2 d1 d0 st72c171 101/152 table 19. spi register map and reset values address (hex.) register name 76543210 21 dr reset value d7 - d6 - d5 - d4 - d3 - d2 - d1 - d0 - 22 cr reset value spie 0 spe 0 - 0 mstr 0 cpol x cpha x spr1 x spr0 x 23 sr reset value spif 0 wcol 0 - 0 modf 0 - 0 - 0 - 0 - 0 st72c171 102/152 7.9 8-bit a/d converter (adc) 7.9.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control/status register. 7.9.2 main features n 8-bit conversion n up to 16 channels with multiplexed input n linear successive approximation n data register (dr) which contains the results n conversion complete status flag n on/off bit (to reduce consumption) the block diagram is shown in figure 55 . 7.9.3 functional description 7.9.3.1 analog power supply v dda and v ssa are the high and low level refer- ence voltage pins. in some devices (refer to device pin out description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. see electrical characteristics section for more de- tails. figure 55. adc block diagram ch2 ch1 ch3 coco 0 adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux r adc c adc d2 d1 d3 d7 d6 d5 d4 d0 adcdr 4 div 2 f adc f cpu hold control st72c171 103/152 8-bit a/d converter (adc) (contd) 7.9.3.2 digital a/d conversion result the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than or equal to v dda (high-level voltage reference) then the conversion result in the dr register is ffh (full scale) without overflow indication. if input voltage (v ain ) is lower than or equal to v ssa (low-level voltage reference) then the con- version result in the dr register is 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdr register. the accuracy of the conversion is described in the parametric section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 7.9.3.3 a/d conversion phases the a/d conversion is based on two conversion phases as shown in figure 56 : n sample capacitor loading [duration: t load ] during this phase, the v ain input voltage to be measured is loaded into the c adc sample capacitor. n a/d conversion [duration: t conv ] during this phase, the a/d conversion is computed (8 successive approximations cycles) and the c adc sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. while the adc is on, these two phases are contin- uously repeated. at the end of each conversion, the sample capaci- tor is kept loaded with the previous measurement load. the advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 7.9.3.4 software procedure refer to the control/status register (csr) and data register (dr) in section 9.9.6 for the bit definitions and to figure 56 for the timings. adc configuration the total duration of the a/d conversion is 12 adc clock periods (1/f adc =2/f cpu ). the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the csr register: C select the ch[3:0] bits to assign the analog channel to be converted. adc conversion in the csr register: C set the adon bit to enable the a/d converter and to start the first conversion. from this time on, the adc performs a continuous conver- sion of the selected channel. when a conversion is complete C the coco bit is set by hardware. C no interrupt is generated. C the result is in the dr register and remains valid until the next conversion has ended. a write to the csr register (with adon set) aborts the current conversion, resets the coco bit and starts a new conversion. figure 56. adc conversion timings 7.9.4 low power modes note : the a/d converter may be disabled by reset- ting the adon bit. this feature allows reduced power consumption when no conversion is needed and between single shot conversions. 7.9.5 interrupts none mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d con- verter requires a stabilisation time before ac- curate conversions can be performed. adccsr write adon coco bit set t load t conv operation hold control st72c171 104/152 8-bit a/d converter (adc) (contd) 7.9.6 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7 = coco conversion complete this bit is set by hardware. it is cleared by soft- ware reading the result in the dr register or writing to the csr register. 0: conversion is not complete 1: conversion can be read from the dr register bit 6 = reserved. must always be cleared. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on bit 4 = reserved. must always be cleared. bit 3:0 = ch[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *note : the number of pins and the channel selec- tion varies according to the device. refer to the de- vice pinout. data register (dr) read only reset value: 0000 0000 (00h) bit 7:0 = d[7:0] analog converted value this register contains the converted analog value in the range 00h to ffh. note : reading this register reset the coco flag. 70 coco 0 adon 0 ch3 ch2 ch1 ch0 channel pin* ch3 ch2 ch1 ch0 ain0 0 0 0 0 ain1 0 0 0 1 ain2 0 0 1 0 ain3 0 0 1 1 ain4 0 1 0 0 ain5 0 1 0 1 ain6 0 1 1 0 ain7 0 1 1 1 ain8 1 0 0 0 ain9 1 0 0 1 ain10 1 0 1 0 ain11 1 0 1 1 ain12 1 1 0 0 ain13 1 1 0 1 ain14 1 1 1 0 ain15 1 1 1 1 70 d7 d6 d5 d4 d3 d2 d1 d0 st72c171 105/152 table 20. adc register map address (hex.) register name 765 4 3210 0070h dr reset value ad7 0 ad6 0 ad5 0 ad4 0 ad3 0 ad2 0 ad1 0 ad0 0 0071h csr reset value coco 0 extck 0 adon 0 0 0 ch3 0 ch2 0 ch1 0 ch0 0 st72c171 106/152 8 instruction set 8.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: C long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. C short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 21. st7 addressing mode overview note 1. at the time the instruction is executed, the program counter (pc) points to the instruction follow- ing jrxx. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 1) + 1 relative indirect jrne [$10] pc-128/pc+127 1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 st72c171 107/152 st7 addressing modes (contd) 8.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 8.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 8.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 8.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 8.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations st72c171 108/152 st7 addressing modes (contd) 8.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 22. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 8.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in memory, of which the ad- dress follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtrac- tion operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/ indirect instructions function jrxx conditional jump callr call relative st72c171 109/152 8.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four bytes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, di- rect bit, or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruc- tion using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret code condition flag modification sim rim scf rcf st72c171 110/152 instruction groups (contd) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > st72c171 111/152 instruction groups (contd) mnemo description function/example dst src h i n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z st72c171 112/152 9 electrical characteristics 9.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 9.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 s ). 9.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd =5v (for the 4.5v v dd 5.5v voltage range) and v dd =3.3v (for the 3v v dd 4v voltage range). they are given only as design guidelines and are not tested. 9.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 57 . figure 57. pin loading conditions 9.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 58 . figure 58. pin input voltage c l st7 pin v in st7 pin st72c171 113/152 9.2 absolute maximum ratings stresses above those listed as absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 9.2.1 voltage characteristics 9.2.2 current characteristics 9.2.3 thermal characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k w for reset , 10k w for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative injection is induced by v in st72c171 115/152 operating conditions (contd) 9.3.2 operating conditions with low voltage detector (lvd) subject to general operating conditions for v dd , f osc , and t a . figure 60. high lvd threshold versus v dd and f osc for flash devices 3) figure 61. medium lvd threshold versus v dd and f osc for flash devices 3) figure 62. low lvd threshold versus v dd and f osc for flash devices 2)4) notes: 1. lvd typical data are based on t a =25c. they are given only as design guidelines and are not tested. 2. data based on characterization results, not tested in production. 3. the v dd rise time rate condition is needed to insure a correct device power-on and lvd reset. not tested in production. 4. if the low lvd threshold is selected, when v dd falls below 3.2v, (v dd minimum operating voltage), the device is guar- anteed to continue functioning until it goes into reset state. the specified v dd min. value is necessary in the device power on phase, but during a power down phase or voltage drop the device will function below this min. level. symbol parameter conditions min typ 1) max unit v it+ reset release threshold (v dd rise) high threshold med. threshold low threshold 4.10 2) 3.75 2) 3.25 2) 4.30 3.90 3.35 4.50 4.05 3.45 v v it- reset generation threshold (v dd fall) high threshold med. threshold low threshold 4) 3.85 2) 3.50 2) 3.00 4.05 3.65 3.10 4.25 3.80 3.20 v hyst lvd voltage threshold hysteresis v it+ -v it- 200 250 300 mv vt por v dd rise time rate 3) 0.2 50 v/ms t g(vdd) filtered glitch delay on v dd 2) not detected by the lvd 40 ns f osc [mhz] supply voltage [v] 16 8 0 2.5 3 3.5 4 4.5 5 5.5 functional area device under functionality and reset not guaranteed in this area for temperatures higher than 85c reset in this area functionality not guaranteed in this area v it- 3 3.85 f osc [mhz] supply voltage [v] 16 8 0 2.5 3 v it- 3 3.5v 4 4.5 5 5.5 functional area device under functionality and reset not guaranteed in this area for temperatures higher than 85c reset in this area functionality not guaranteed in this area f osc [mhz] supply voltage [v] 16 8 0 2.5 v it- 3 3 3.5 4 4.5 5 5.5 functional area device under functionality not guaranteed in this area for temperatures higher than 85c reset in this area functionality not guaranteed in this area st72c171 116/152 9.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode for which the clock is stopped). 9.4.1 run and slow modes figure 63. typical idd in run vs. fcpu figure 64. typical i dd in slow vs. f cpu notes: 1. typical data are based on t a =25c, v dd =5v (4.5v v dd 5.5v range) and v dd =3.4v (3.2v v dd 3.6v range). 2. data based on characterization results, tested in production at v dd max. and f cpu max. 3. cpu running with memory access, all i/o pins in output mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, css and lvd disabled. 4. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, css and lvd disabled. symbol parameter conditions max unit d i dd( d ta) supply current variation vs. temperature constant v dd and f cpu 10 % symbol parameter conditions typ 1) max 2) unit i dd supply current in run mode 3) (see figure 63 ) 4.5v v dd 5.5v f osc =1mhz, f cpu =500khz f osc =4mhz, f cpu =2mhz f osc =16mhz, f cpu =8mhz 500 1500 5600 900 2500 9000 m a supply current in slow mode 4) (see figure 64 ) f osc =1mhz, f cpu =31.25khz f osc =4mhz, f cpu =125khz f osc =16mhz, f cpu =500khz 150 250 670 450 550 1250 supply current in run mode 3) (see figure 63 ) 3.2v v dd 3.6v f osc =1mhz, f cpu =500khz f osc =4mhz, f cpu =2mhz f osc =16mhz, f cpu =8mhz 300 970 3600 550 1350 4500 supply current in slow mode 4) (see figure 64 ) f osc =1mhz, f cpu =31.25khz f osc =4mhz, f cpu =125khz f osc =16mhz, f cpu =500khz 100 170 420 250 300 700 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 1 2 3 4 5 6 7 idd [ma] 8mhz 4mhz 2mhz 500khz 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 idd [ma] 500khz 250khz 125khz 31.25khz st72c171 117/152 supply current characteristics (contd) 9.4.2 wait and slow wait modes figure 65. typical i dd in wait vs. f cpu figure 66. typical i dd in slow-wait vs. f cpu notes: 1. typical data are based on t a =25c, v dd =5v (4.5v v dd 5.5v range) and v dd =3.4v (3.2v v dd 3.6v range). 2. data based on characterization results, tested in production at v dd max. and f cpu max. 3. all i/o pins in output mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, css and lvd disabled. 4. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, css and lvd disabled. symbol parameter conditions typ 1) max 2) unit i dd supply current in wait mode 3) (see figure 65 ) 4.5v v dd 5.5v f osc =1mhz, f cpu =500khz f osc =4mhz, f cpu =2mhz f osc =16mhz, f cpu =8mhz 150 560 2200 280 900 3000 m a supply current in slow wait mode 4) (see figure 66 ) f osc =1mhz, f cpu =31.25khz f osc =4mhz, f cpu =125khz f osc =16mhz, f cpu =500khz 20 90 340 70 190 850 supply current in wait mode 3) (see figure 65 ) 3.2v v dd 3.6v f osc =1mhz, f cpu =500khz f osc =4mhz, f cpu =2mhz f osc =16mhz, f cpu =8mhz 90 350 1370 200 550 1900 supply current in slow wait mode 4) (see figure 66 ) f osc =1mhz, f cpu =31.25khz f osc =4mhz, f cpu =125khz f osc =16mhz, f cpu =500khz 10 50 200 20 80 350 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 0.5 1 1.5 2 2.5 3 idd [ma] 8mhz 4mhz 2mhz 500khz 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 idd [ma] 500khz 250khz 125khz 31.25khz st72c171 118/152 supply current characteristics (contd) 9.4.3 halt mode 9.4.4 supply and clock managers the previous current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode). 9.4.5 on-chip peripherals notes: 1. typical data are based on t a =25c. 2. all i/o pins in input mode with a static value at v dd or v ss (no load), css and lvd disabled. data based on charac- terization results, tested in production at v dd max. and f cpu max. 3. data based on characterization results, not tested in production. 4. data based on characterization results done with the external components specified in section 9.5.3 and section 9.5.4 , not tested in production. 5. as the oscillator is based on a current source, the consumption does not depend on the voltage. 6. data based on a differential i dd measurement between reset configuration (timer counter running at f cpu /4) and timer counter stopped (selecting external clock capability). data valid for one timer. 7. data based on a differential i dd measurement between reset configuration and a permanent spi master communica- tion (data sent equal to 55h). 8. data based on a differential i dd measurement between reset configuration and i2c peripheral enabled (pe bit set). 9. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. symbol parameter conditions typ 1) max unit i dd supply current in halt mode 2) v dd =5.5v -40c t a +85c 0 10 m a v dd =3.6v -40c t a +85c 6 symbol parameter conditions typ 1) max 3) unit i dd(ck) supply current of internal rc oscillator 500 750 m a supply current of external rc oscillator 4) 525 750 supply current of resonator oscillator 4) & 5) lp: low power oscillator mp: medium power oscillator ms: medium speed oscillator hs: high speed oscillator 200 300 450 700 400 550 750 1000 clock security system supply current 150 350 i dd(lvd) lvd supply current halt mode 100 150 symbol parameter conditions typ unit i dd(tim) 16-bit timer supply current 6) f cpu =8mhz v dd = 3.4v 50 m a v dd = 5.0v 150 i dd(spi) spi supply current 7) f cpu =8mhz v dd = 3.4v 250 v dd = 5.0v 350 i dd(i2c) i 2 c supply current 8) f cpu =8mhz v dd = 3.4v 250 v dd = 5.0v 350 i dd(adc) adc supply current when converting 9) f adc =4mhz v dd = 3.4v 800 v dd = 5.0v 1100 st72c171 119/152 9.5 clock and timing characteristics subject to general operating conditions for v dd , f osc , and t a . 9.5.1 general timings 9.5.2 external clock source figure 67. typical application with an external clock source notes: 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. d t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 3. data based on design simulation and/or technology characteristics, not tested in production. symbol parameter conditions min typ 1) max unit t c(inst) instruction cycle time 2 3 12 t cpu f cpu =8mhz 250 375 1500 ns t v(it) interrupt reaction time 2) t v(it) = d t c(inst) + 10 10 22 t cpu f cpu =8mhz 1.25 2.75 m s symbol parameter conditions min typ max unit v osc1h osc1 input pin high level voltage see figure 67 0.7xv dd v dd v v osc1l osc1 input pin low level voltage v ss 0.3xv dd t w(osc1h) t w(osc1l) osc1 high or low time 3) 15 ns t r(osc1) t f(osc1) osc1 rise or fall time 3) 15 i l oscx input leakage current v ss v in v dd 1 m a osc1 osc2 f osc external st72xxx clock source not connected internally v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i l 90% 10% st72c171 120/152 clock and timing characteristics (contd) 9.5.3 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. all the information given in this paragraph are based on characterization results with specified typical external componants. in the application, the reso- nator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabiliza- tion time. refer to the crystal/ceramic resonator manufacturer for more details (frequency, pack- age, accuracy...). figure 68. typical application with a crystal or ceramic resonator notes: 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. t su(osc) is the typical oscillator start-up time measured between v dd =2.8v and the fetch of the first instruction (with a quick v dd ramp-up from 0 to 5v (<50 m s). 3. the oscillator selection can be optimized in terms of supply current using an high quality resonator with small r s value. refer to crystal/ceramic resonator manufacturer for more details. symbol parameter conditions min max unit f osc oscillator frequency 3) lp: low power oscillator mp: medium power oscillator ms: medium speed oscillator hs: high speed oscillator 1 >2 >4 >8 2 4 8 16 mhz r f feedback resistor 20 40 k w c l1 c l2 recommanded load capacitances ver- sus equivalent serial resistance of the crystal or ceramic resonator (r s ) r s =200 w lp oscillator r s =200 w mp oscillator r s =200 w ms oscillator r s =100 w hs oscillator 38 32 18 15 56 46 26 21 pf i 2 osc2 driving current v dd =5v lp oscillator v in =v ss mp oscillator ms oscillator hs oscillator 40 50 100 250 130 300 550 820 m a oscil. typical crystal or ceramic resonators c l1 [pf] c l2 [pf] t su(osc) [ms] 2) reference freq. characteristic 1) crystal lp jauch s-200-30-30/50 2mhz d f osc =[30ppm 25c ,30ppm d ta ] , typ. r s =200 w 33 34 10~15 mp ss3-400-30-30/30 4mhz d f osc =[30ppm 25c ,30ppm d ta ] , typ. r s =60 w 33 34 7~10 ms ss3-800-30-30/30 8mhz d f osc =[30ppm 25c ,30ppm d ta ] , typ. r s =25 w 33 34 2.5~3 hs ss3-1600-30-30/30 16mhz d f osc =[30ppm 25c ,30ppm d ta ] , typ. r s =15 w 33 34 1~1.5 ceramic lp murata csa2.00mg 2mhz d f osc =[0.5% tolerance ,0.3% d ta , 0.3% aging , x.x% correl ] 33 30 4.2 mp csa4.00mg 4mhz d f osc =[0.5% tolerance ,0.3% d ta , 0.3% aging , x.x% correl ] 33 30 2.1 ms csa8.00mtz 8mhz d f osc =[0.5% tolerance ,0.5% d ta , 0.3% aging , x.x% correl ] 33 30 1.1 hs csa16.00mxz040 16mhz d f osc =[0.5% tolerance ,0.3% d ta , 0.3% aging , x.x% correl ] 33 30 0.7 osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator when resonator with integrated capacitors st72c171 121/152 clock characteristics (contd) 9.5.4 rc oscillators the st7 internal clock can be supplied with an rc oscillator. this oscillator can be used with internal or external components (selectable by option byte). figure 69. typical application with rc oscillator figure 70. typical internal rc oscillator figure 71. typical external rc oscillator notes: 1. data based on characterization results. 2. guaranteed frequency range with the specified c ex and r ex ranges taking into account the device process variation. data based on design simulation. 3. data based on characterization results done with v dd nominal at 5v, not tested in production. 4. r ex must have a positive temperature coefficient (ppm/c), carbon resistors should therefore not be used. 5. important: when no external c ex is applied, the capacitance to be considered is the global parasitic capacitance which is subject to high variation (package, application...). in this case, the rc oscillator frequency tuning has to be done by trying out several resistor values. symbol parameter conditions min typ max unit f osc internal rc oscillator frequency 1) see figure 69 3.60 5.10 mhz external rc oscillator frequency 2) 114 t su(osc) internal rc oscillator start-up time 3) 2.0 ms external rc oscillator start-up time 3) r ex =47k w, c ex =0pf r ex =47k w, c ex =100pf r ex =10k w, c ex =6.8pf r ex =10k w, c ex =470pf 1.0 6.5 0.7 3.0 r ex oscillator external resistor 4) see figure 70 10 47 k w c ex oscillator external capacitor 0 5) 470 pf osc2 osc1 f osc c ex r ex external rc internal rc v ref + - v dd current copy voltage generator c ex discharge st72xxx 3.2 5.5 vdd [v] 3.85 3.9 3.95 4 4.05 4.1 4.15 4.2 4.25 fosc [mhz] -40c +25c +85c 0 6.8 22 47 100 270 470 cex [pf] 0 5 10 15 20 fosc [mhz] rex=10kohm rex=15kohm rex=22kohm rex=33kohm rex=39kohm rex=47kohm st72c171 122/152 clock characteristics (contd) 9.5.5 clock security system (css) figure 72. typical safe oscillator frequencies note: 1. data based on characterization results, tested in production between 90khz and 500khz. 2. filtered glitch on the f osc signal. see functional description in section 4.3 on page 21 for more details. symbol parameter conditions min typ max unit f sfosc safe oscillator frequency 1) t a = 25c, v dd = 5.0v 250 340 430 khz t a = 25c, v dd = 3.4v 190 260 330 f gfosc glitch filtered frequency 2) 30 mhz 3.2 5.5 vdd [v] 200 250 300 350 400 fosc [khz] -40c +25c +85c st72c171 123/152 9.6 memory characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. 9.6.1 ram and hardware registers 9.6.2 flash program memory notes: 1. minimum v dd supply voltage without losing data stored in ram (in in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by construction, not tested in production. 2. data based on characterization results, tested in production at t a =25c. 3. up to 16 bytes can be programmed at a time for a 4kbytes flash block (then up to 32 bytes at a time for an 8k device) 4. the data retention time increases when the t a decreases. 5. data based on reliability test results and monitored in production. symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 1.6 v symbol parameter conditions min typ max unit t a(prog) programming temperature range 2) 02570 c t prog programming time for 1~16 bytes 3) t a = +25c 8 25 ms programming time for 4 or 8kbytes t a = +25c 2.1 6.4 sec t ret data retention 5) t a =+55c 4) 20 years n rw write erase cycles 5) t a = +25c 100 cycles st72c171 124/152 9.7 emc characteristics susceptibility tests are performed on a sample ba- sis during product characterization. 9.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). C esd: electro-static discharge (positive and neg- ative) is applied on all pins of the device until a functional disturbance occurs. this test con- forms with the iec 1000-4-2 standard. C ftb: a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. figure 73. emc recommended star network power supply connection 2) notes: 1. data based on characterization results, not tested in production. 2. the suggested 10nf and 0.1 m f decoupling capacitors on the power supply lines are proposed as a good price vs. emc performance tradeoff. they have to be put as close as possible to the device power supply pins. other emc recommen- dations are given in other sections (i/os, reset, oscx pin characteristics). symbol parameter conditions neg 1) pos 1) unit v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-2 -1 1 kv v fftb fast transient voltage burst limits to be ap- plied through 100pf on v dd and v dd pins to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-4 -4 4 v dd v ss 0.1 m f 10nf v dd st72xxx v ssa v dda 0.1 m f power supply source st7 digital noise filtering external noise filtering st72c171 125/152 emc characteristics (contd) 9.7.2 absolute electrical sensitivity based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, re- fer to the an1181 st7 application note. 9.7.2.1 electro-static discharge (esd) electro-static discharges (3 positive then 3 nega- tive pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). two models are usually simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. see figure 74 and the following test sequences. human body model test sequence C c l is loaded through s1 by the hv pulse gener- ator. C s1 switches position from generator to r. C a discharge from c l through r (body resistance) to the st7 occurs. C s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. machine model test sequence C c l is loaded through s1 by the hv pulse gener- ator. C s1 switches position from generator to st7. C a discharge from c l to the st7 occurs. C s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. C r (machine resistance), in series with s2, en- sures a slow discharge of the st7. absolute maximum ratings figure 74. typical equivalent esd circuits notes: 1. data based on characterization results, not tested in production. symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 2000 v v esd(mm) electro-static discharge voltage (machine model) t a = +25c 200 st7 s2 r=1500 w s1 high voltage c l = 100pf pulse generator st7 s2 high voltage c l = 200pf pulse generator r=10k~10m w s1 human body model machine model st72c171 126/152 emc characteristics (contd) 9.7.2.2 static and dynamic latch-up C lu: 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power sup- ply pin), a current injection (applied to each input, output and configurable i/o pin) and a power supply switch sequence are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the an1181 st7 application note. C dlu: electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in re- set mode. this test conforms to the iec1000-4-2 and saej1752/3 standards and is described in figure 75 . for more details, refer to the an1181 st7 application note. electrical sensitivities figure 75. simplified diagram of the esd generator for dlu notes: 1. class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). 2. schaffner nsg435 with a pointed test finger. symbol parameter conditions class 1) lu static latch-up class t a = +25c t a = +85c a a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c a r ch =50m w r d =330 w c s = 150pf esd hv relay discharge tip discharge return connection generator 2) st7 v dd v ss st72c171 127/152 emc characteristics (contd) 9.7.3 esd pin protection strategy to protect an integrated circuit against electro- static discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. the stress generally affects the circuit el- ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. the elements to be pro- tected must not receive excessive current, voltage or heating within their structure. an esd network combines the different input and output esd protections. this network works, by al- lowing safe discharge paths for the pins subjected to esd stress. two critical esd stress cases are presented in figure 76 and figure 77 for standard pins and in figure 78 and figure 79 for true open drain pins. standard pin protection to protect the output structure the following ele- ments are added: C a diode to v dd (3a) and a diode from v ss (3b) C a protection device between v dd and v ss (4) to protect the input structure the following ele- ments are added: C a resistor in series with the pad (1) C a diode to v dd (2a) and a diode from v ss (2b) C a protection device between v dd and v ss (4) figure 76. positive stress on a standard pad vs. v ss figure 77. negative stress on a standard pad vs. v dd in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path path to avoid in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path st72c171 128/152 emc characteristics (contd) true open drain pin protection the centralized protection (4) is not involved in the discharge of the esd stresses applied to true open drain pads due to the fact that a p-buffer and diode to v dd are not implemented. an additional local protection between the pad and v ss (5a & 5b) is implemented to completly absorb the posi- tive esd discharge. multisupply configuration when several types of ground (v ss , v ssa , ...) and power supply (v dd , v dda , ...) are available for any reason (better noise immunity...), the structure shown in figure 80 is implemented to protect the device against esd. figure 78. positive stress on a true open drain pad vs. v ss figure 79. negative stress on a true open drain pad vs. v dd figure 80. multisupply configuration in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path path to avoid (5a) (5b) in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path (3b) (3b) v dda v ssa v dda v dd v ss back to back diode between grounds v ssa st72c171 129/152 9.8 i/o port pin characteristics 9.8.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 81. two typical applications with unused i/o pin figure 82. typical i pu vs. v dd with v in =v ss notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor (see figure 81 ). data based on design simulation and/or technology characteristics, not tested in production. 5. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics de- scribed in figure 82 ). this data is based on characterization results, tested in production at v dd max. 6. data based on characterization results, not tested in production. 7. to generate an external interrupt, a minimum pulse width has to be applied on an i/o port pin configured as an external interrupt source. symbol parameter conditions min typ 1) max unit v il input low level voltage 2) 0.3xv dd v v ih input high level voltage 2) 0.7xv dd v hys schmitt trigger voltage hysteresis 3) 400 mv i l input leakage current v ss v in v dd 1 m a i s static current consumption 4) floating input mode 200 r pu weak pull-up equivalent resistor 5) v in = v ss v dd =5v 70 120 250 k w v dd =3.3v 170 200 230 c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time 6) c l =50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time 6) 25 t w(it)in external interrupt pulse time 7) 1t cpu 10k w unused i/o port st72xxx 10k w unused i/o port st72xxx v dd 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 10 20 30 40 50 60 70 ipu [a] ta=-40c ta=25c ta=85c st72c171 130/152 i/o port pin characteristics (contd) 9.8.2 output driving current subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 83. typical v ol at v dd =5v (standard) figure 84. typical v ol at v dd =5v (high-sink) figure 85. typical v dd -v oh at v dd =5v notes: 1. the i io current sunk must always respect the absolute maximum rating specified in section 9.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect the absolute maximum rating specified in section 9.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . symbol parameter conditions min max unit v ol 1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 83 and figure 86 ) v dd =5v i io =+5ma 1.2 v i io =+2ma 0.5 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 85 and figure 87 ) i io =+20ma 1.5 i io =+8ma 0.6 v oh 2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 86 and figure 88 ) i io =-5ma v dd -1.8 i io =-2ma v dd -0.7 0246810 iio [ma] 0 0.5 1 1.5 2 vol [v] at vdd=5v ta=-40c ta=25c ta=85c 0 5 10 15 20 25 30 iio [ma] 0 0.5 1 1.5 vol [v] at vdd=5v ta=-40c ta=25c ta=85c -8 -6 -4 -2 0 iio [ma] 2 2.5 3 3.5 4 4.5 5 5.5 vdd-voh [v] at vdd=5v ta=-40c ta=25c ta=85c st72c171 131/152 i/o port pin characteristics (contd) figure 86. typical v ol vs. v dd (standard i/os) figure 87. typical v ol vs. v dd (high-sink i/os) figure 88. typical v dd -v oh vs. v dd 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.2 0.25 0.3 0.35 0.4 0.45 vol [v] at iio=2ma ta=-40c ta=25c ta=85c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 vol [v] at iio=5ma ta=-40c ta=25c ta=85c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.2 0.25 0.3 0.35 0.4 0.45 0.5 vol [v] at iio=8ma ta=-40c ta=25c ta=85c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 vol [v] at iio=20ma ta=-40c ta=25c ta=85c 3.5 4 4.5 5 5.5 vdd [v] 0 1 2 3 4 5 vdd-voh [v] at iio=-5ma ta=-40c ta=25c ta=85c 3.2 3.5 4 4.5 5 5.5 vdd [v] 2 2.5 3 3.5 4 4.5 5 5.5 vdd-voh [v] at iio=-2ma ta=-40c ta=25c ta=85c st72c171 132/152 9.9 control pin characteristics 9.9.1 asynchronous reset pin subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 89. typical application with reset pin 8) notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. the i io current sunk must always respect the absolute maximum rating specified in section 9.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 5. the r on pull-up equivalent resistor is based on a resistive transistor (corresponding i on current characteristics de- scribed in figure 90 ). this data is based on characterization results, not tested in production. 5. to guarantee the reset of the device, a minimum pulse has to be applied to reset pin. 6. all short pulse applied on reset pin with a duration below t h(rstl)in can be ignored. 7. the reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy environment. 8. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). symbol parameter conditions min typ 1) max unit v il input low level voltage 2) 0.3xv dd v v ih input high level voltage 2) 0.7xv dd v hys schmitt trigger voltage hysteresis 3) 400 mv v ol output low level voltage 4) (see figure 91 , figure 92 ) v dd =5v i io =+5ma 0.68 0.95 v i io =+2ma 0.28 0.45 r on weak pull-up equivalent resistor 5) v in = v ss v dd =5v 20 40 60 k w v dd =3.4v 80 100 120 t w(rstl)out generated reset pulse duration external pin or internal reset sources 6 30 1/f sfosc m s t h(rstl)in external reset pulse hold time 6) 20 m s t g(rstl)in filtered glitch duration 7) 100 ns reset v dd watchdog reset st72xxx lvd reset internal r on 0.1 m f v dd 0.1 m f v dd 4.7k w external reset circuit 8) reset control option a l user st72c171 133/152 control pin characteristics (contd) figure 90. typical i on vs. v dd with v in =v ss figure 91. typical v ol at v dd =5v (reset ) figure 92. typical v ol vs. v dd (reset ) 3.2 3.5 4 4.5 5 5.5 vdd [v] 0 50 100 150 200 ion [a] ta=-40c ta=25c ta=85c 0 1234 5678 iio [ma] 0 0.5 1 1.5 vol [v] at vdd=5v ta=-40c ta=25c ta=85c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.15 0.2 0.25 0.3 0.35 0.4 0.45 vol [v] at iio=2ma ta=-40c ta=25c ta=85c 3.2 3.5 4 4.5 5 5.5 vdd [v] 0.4 0.6 0.8 1 1.2 vol [v] at iio=5ma ta=-40c ta=25c ta=85c st72c171 134/152 control pin characteristics (contd) 9.9.2 ispsel pin subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 93. two typical applications with ispsel pin 2) notes: 1. data based on design simulation and/or technology characteristics, not tested in production. 2. when the isp remote mode is not required by the application ispsel pin must be tied to v ss . symbol parameter conditions min max unit v il input low level voltage 1) v ss 0.2 v v ih input high level voltage 1) v dd -0.1 12.6 i l input leakage current v in =v ss 1 m a ispsel st72xxx 10k w programming tool ispsel st72xxx st72c171 135/152 9.10 timer peripheral characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output...). 9.10.1 watchdog timer 9.10.2 8-bit pwm auto-reload timer 9.10.3 16-bit timer symbol parameter conditions min typ max unit t w(wdg) watchdog time-out duration 12,288 786,432 t cpu f cpu =8mhz 1.54 98.3 ms symbol parameter conditions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 1t cpu f cpu =8mhz 125 ns f ext timer external clock frequency 0 f cpu /2 mhz f pwm pwm repetition rate 0 f cpu /2 mhz res pwm pwm resolution 8 bit symbol parameter conditions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 2t cpu f cpu =8mhz 250 ns f ext timer external clock frequency 0 f cpu /4 mhz f pwm pwm repetition rate 0 f cpu /4 mhz res pwm pwm resolution 16 bit st72c171 136/152 9.11 communication interface characteristics 9.11.1 spi - serial peripheral interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). figure 94. spi slave timing diagram with cpha=0 3) notes: 1. data based on design simulation and/or characterisation results, not tested in production. 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 0.0625 f cpu /4 2 mhz slave f cpu =8mhz 0 f cpu /2 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss ) ss setup time slave 120 ns t h(ss ) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 120 t h(so) data output hold time 0 t v(mo) data output valid time master (before capture edge) 0.25 t cpu t h(mo) data output hold time 0.25 ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out seenote2 cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in st72c171 137/152 communication interface characteristics (contd) figure 95. spi slave timing diagram with cpha=1 1) figure 96. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in msb out bit6 in bit6 out lsb out lsb in see note 2 seenote2 cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck) st72c171 138/152 communications interface characteristics (contd) 9.11.2 sci - serial communications interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (rdi and tdo). symbol parameter conditions standard baud rate unit f cpu accuracy vs. standard prescaler f tx f rx communication frequency 8mhz ~0.16% conventional mode tr (or rr)=64, pr=13 tr (or rr)=16, pr=13 tr (or rr)= 8, pr=13 tr (or rr)= 4, pr=13 tr (or rr)= 2, pr=13 tr (or rr)= 8, pr= 3 tr (or rr)= 1, pr=13 300 1200 2400 4800 9600 10400 19200 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 hz extended mode etpr (or erpr) = 13 38400 ~38461.54 ~0.79% extended mode etpr (or erpr) = 35 14400 ~14285.71 st72c171 139/152 9.12 8-bit adc characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 97. typical application with adc notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2. when v dda and v ssa pins are not available on the pinout, the adc refer to v dd and v ss . 3. any added external serial resistor will downgrade the adc accuracy (especially for resistance greater than 10k w ). data based on characterization results, not tested in production. 4. the stabilization time of the ad converter is masked by the first t load . the first conversion after the enable is then always valid. symbol parameter conditions min typ 1) max unit f adc adc clock frequency 4 mhz v ain conversion range voltage 2) v ssa v dda v r ain external input resistor 10 3) k w c adc internal sample and hold capacitor 6 pf t stab stabilization time after adc enable f cpu =8mhz, f adc =4mhz 0 4) m s t adc conversion time (sample+hold) 3 - sample capacitor loading time - hold conversion time 4 8 1/f adc ainx st72xxx c io ~2pf v dd i l 1 m a v t 0.6v v t 0.6v v ain r ain v dda v ssa 0.1 m f v dd adc st72c171 140/152 8-bit adc characteristics (contd) adc accuracy figure 98. adc accuracy characteristics notes: 1. adc accuracy vs. negative injection current: for i inj- =0.8ma, the typical leakage induced inside the die is 1.6a and the effect on the adc accuracy is a loss of 1 lsb for each 10k w increase of the external analog source impedance. this effect on the adc accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an input with analog capability, adjacent to the enabled analog input - at 5v v dd supply, and worst case temperature. 3. data based on characterization results over the whole temperature range, monitored in production. symbol parameter conditions min max unit |e t | total unadjusted error 1) v dd =5.0v, 3) f cpu =8mhz 1 lsb e o offset error 1) -0.5 0.5 e g gain error 1) -0.5 0.5 |e d | differential linearity error 1) 0.5 |e l | integral linearity error 1) 0.5 e o e g 1lsb ideal 1lsb ideal v dda v ssa C 256 ---------------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 255 254 253 5 4 3 2 1 0 7 6 1234567 253 254 255 256 (1) (2) e t e d e l (3) v dda v ssa st72c171 141/152 9.13 op-amp module characteristics these op-amp specific values take precedence over any generic values given elsewhere in the docu- ment. (t =25 o c, v dd - v ss = 5 v ). 1) a vcl = closed loop gain (repeater configuration) 2) tested with positve input connected to internal band gap (reference voltage enabled) and negative in- put floating. 3) data based on characterization, not tested in production 4) data guaranteed by design, not tested in production 5) slew rate is the rate of change from 10% to 90% of the output voltage step. spga1 / spga2 - software programmable gain operational amplifiers symbol parameter condition min typ max unit |vio| input offset voltage 3 10 mv i cc supply current per amplifier 2) v dd =5.0v, a vcl =1, no load 1) 0.8 2 ma cmr 3) common mode rejection ratio 70 db svr 3) supply voltage rejection ratio 70 db avd 3) voltage gain (r l =1k w ) 100 v/mv v oh high level ouput voltage (r l =10k w) v dd =5v 4.9 v v ol low level ouput voltage (r l =10k w) v dd =5v 0.10 v i sc 3) short circuit current sourced short circuit current sunk vo= 5v connected to v ss vo= 0v connected to v dd 45 70 ma ma gpb gain bandwidth product 4 mhz sr + slew rate 5) a vcl =1 1) 1v/ m s sr - slew rate 5) a vcl =1 1) 1v/ m s en 3) thermal noise 50 f m 3) phase margin 40 55 degrees cin 4) input capacitance 10 pf v icm 4) common mode input voltage range v ss - 0.2 v dd +0.2 v d vref reference voltage (v dda /8 step) precision 10 % d v bg band gap precision 10 % d gain programmable gain precision 10 % nv hz 1 C st72c171 142/152 op-amp module characteristics (contd) 1) a vcl = closed loop gain (repeater configuration) 2) data based on characterization, not tested in production 3) data guaranteed by design, not tested in production 4) slew rate is the rate of change from 10% to 90% of the output voltage step. oa3 operational amplifier symbol parameter condition min typ max unit |vio| input offset voltage 3 10 mv i cc supply current per amplifier v dd =5.0v, a vcl =1, no load 1) 300 500 a cmr 2) common mode rejection ratio 70 db svr 2) supply voltage rejection ratio 70 db avd 2) voltage gain (r l =1k w ) 100 v/mv v oh high level ouput voltage (r l =10k w) v dda =5v 4.9 v v ol low level ouput voltage (r l =10k w) v dda =5v 0.10 v i sc 2) short circuit current sourced short circuit current sunk vo= 1 connected to v ss vo= 0 connected to v dd 45 70 ma ma gpb gain bandwidth product 6 mhz sr + slew rate 4) a vcl =1 1) 1v/ m s sr - slew rate 4) a vcl =1 1) 1v/ m s en 2) thermal noise 50 f m 2) phase margin 40 55 degrees cin 3) input capacitance 10 pf v icm 3) common mode input voltage range v ss - 0.2 v dd +0.2 v nv hz 1 C st72c171 143/152 9.13.1 typical phase gain vs. frequency figure 99. gain vs frequency 9.13.2 typical total harmonic distorsion figure 100 shows three typical curves for different v dd values. this characterisation has been done at t a 25c using a 1 khz sine wave signal with an average value of v dd /2. this signal is input to the spga configured in non-inverter mode with a gain of 1. the spga output is loaded with a 1k resistor. figure 100. total harmonic distorsion vs vout 1.00e+3 1.00e+4 1.00e+5 1.00e+6 1.00e+7 -40 -20 0 20 40 60 gain (db) -120 -90 -60 -30 0 30 60 90 120 150 180 phase (deg) gain (db) phase (deg) load rl=2kohm cl= 120pf vdd=5v 01234567 vout peak-peak (v) 0 0.05 0.1 0.15 0.2 distorsion(%) vdd=6v vdd=5v vdd=3v rl =10kohm, f= 1khz st72c171 144/152 10 general information 10.1 package mechanical data figure 101. 32-pin shrink plastic dual in line package figure 102. 34-pin small outline dim. mm inches min typ max min typ max a 3.56 3.76 5.08 0.140 0.148 0.200 a1 0.51 0.020 a2 3.05 3.56 4.57 0.120 0.140 0.180 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.76 1.02 1.40 0.030 0.040 0.055 c 0.20 0.25 0.36 0.008 0.010 0.014 d 27.43 27.94 28.45 1.080 1.100 1.120 e 9.91 10.41 11.05 0.390 0.410 0.435 e1 7.62 8.89 9.40 0.300 0.350 0.370 e 1.78 0.070 ea 10.16 0.400 eb 12.70 0.500 l 2.54 3.05 3.81 0.100 0.120 0.150 number of pins n32 1 n b d vr01725j n/2 b1 e a l see lead detail e 1 e 3 a 2 a 1 e c e b e a dim. mm inches min typ max min typ max a 2.46 2.64 0.097 0.104 a1 0.13 0.29 0.005 0.0115 b 0.36 0.48 0.014 0.019 c 0.23 0.32 0.0091 0.0125 d 17.73 18.06 0.698 0.711 e 7.42 7.59 0.292 0.299 e 1.02 0.040 h 10.16 10.41 0.400 0.410 h 0.64 0.74 0.025 0.029 k 0 8 l 0.61 1.02 0.024 0.040 number of pins n34 so34s 0.10mm .004 seating plane st72c171 145/152 10.2 thermal characteristics notes: 1. the power dissipation is obtained from the formula p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation determined by the user. 2. the average chip-junction temperature can be obtained from the formula t j = t a + p d x rthja. symbol ratings value unit r thja package thermal resistance (junction to ambient) sdip32 so34 60 70 c/w p d power dissipation 1) 500 mw t jmax maximum junction temperature 2) 150 c st72c171 146/152 10.3 soldering and glueability information recommended soldering information given only as design guidelines in figure 103 and figure 104 . recommended glue for smd plastic packages dedicated to molding compound with silicone: n heraeus: pd945, pd955 n loctite: 3615, 3298 figure 103. recommended wave soldering profile (with 37% sn and 63% pb) figure 104. recommended reflow soldering oven profile (mid jedec) 10.4 package/socket footprint proposal table 23. suggested list of sdip32 socket types table 24. suggested list of so34 socket types package / probe adaptor / socket reference same footprint socket type sdip32 emu probe textool 232-1291-00 x textool package / probe adaptor / socket reference same footprint socket type so34 emu probe emulator probe includes an adapter with s034 footprint to be sol- dered on user pcb xn/a 250 200 150 100 50 0 40 80 120 160 time [sec] temp. [c] 20 60 100 140 5 sec cooling phase (room temperature) preheating 80c phase soldering phase 250 200 150 100 50 0 100 200 300 400 time [sec] temp. [c] ramp up 2c/sec for 50sec 90 sec at 125c 150 sec above 183c ramp down natural 2c/sec max tmax=220+/-5c for 25 sec st72c171 147/152 11 device configuration and ordering information the device is available for production a user pro- grammable version (flash). flash devices are shipped to customers with a default content (ffh). flash devices have to be configured by the cus- tomer using the option bytes. 11.1 option bytes the two option bytes allow the hardware configu- ration of the microcontroller to be selected. the option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard st7 program- ming tool). the default content of the flash is fixed to ffh. in masked rom devices, the option bytes are fixed in hardware by the rom code (see option list). user option byte 0 bit 7:1 = reserved , must always be 1. bit 1= oa3e op-amp 3 enable this option bit enables or disables the third op- amp of the on-chip op-amp module. 0: oe3 disabled 1: oe3 enabled bit 0 = fmp full memory protection. this option bit enables or disables external access to the internal program memory (read-out protec- tion). clearing this bit causes the erasing (to 00h) of the whole memory (including the option byte). 0: program memory not read-out protected 1: program memory read-out protected user option byte 1 bit 7 = cfc clock filter control on/off this option bit enables or disables the clock filter (cf) features. 0: clock filter enabled 1: clock filter disabled bit 6:4 = osc[2:0] oscillator selection these three option bits can be used to select the main oscillator as shown in table 25 . bit 3:2 = lvd[1:0] low voltage detection selection these option bits enable the lvd block with a se- lected threshold as shown in table 26 . bit 1 = wdg halt watchdog and halt mode this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode bit 0 = wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) table 25. main oscillator configuration table 26. lvd threshold configuration selected oscillator osc2 osc1 osc0 external clock (stand-by) 111 ~4 mhz internal rc 110 1~14 mhz external rc 10x low power resonator (lp) 011 medium power resonator (mp) 010 medium speed resonator (ms) 001 high speed resonator (hs) 000 configuration lvd1 lvd0 lvd off 11 highest voltage threshold ( ~ 4.50v) 10 medium voltage threshold ( ~ 4.05v) 01 lowest voltage threshold ( ~ 3.45v) 00 user option byte 0 70 user option byte 1 70 reserved oa3e fmp cfc osc 2 osc 1 osc 0 lvd1 lvd0 wdg halt wdg sw default value 111111 1 011101111 st72c171 148/152 11.2 device ordering information figure 105. flash user programmable device type device package temp. range 6= industrial -40 to +85 c b= plastic dip m= plastic soic st72c171k2 st72c171 149/152 11.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro- controller family. full details of tools available for the st7 from third party manufacturers can be ob- tain from the stmicroelectronics internet site: http//mcu.st.com. third party tools n actum n bp n cosmic n cmx n data i/o n hitex n hiware n isystem n kanda n leap tools from these manufacturers include c compli- ers, emulators and gang programmers. stmicroelectronics tools two types of development tool are offered by st, all of them connect to a pc via a parallel (lpt) port: see table 27 and table 28 for more details. table 27. stmicroelectronic tool features table 28. dedicated stmicroelectronics development tools note : 1. in-situ programming (isp) interface for flash devices. in-circuit emulation programming capability 1) software included st7 hds2 emulator yes, powerful emulation features including trace/ logic analyzer no st7 cd rom with: C st7 assembly toolchain C stvd7 and wgdb7 powerful source level debugger for win 3.1, win 95 and nt C c compiler demo versions C st realizer for win 3.1 and win 95. C windows programming tools for win 3.1, win 95 and nt st7 programming board no yes (all packages),support also isp 1) supported product st7 hds2 emulator st7 programming board st72c171k2, st7mdt6-emu2b st7mdt6-epb2/eu st7mdt6-epb2/us st7mdt6-epb2/uk st72c171 150/152 11.4 st7 application notes 11.5 to get more information to get the latest information on this product please use the st web server: http://mcu.st.com/ identification description programming and tools an985 executing code in st7 ram an986 using the st7 indirect addressing mode an987 st7 in-circuit programming an988 starting with st7 assembly tool chain an989 starting with st7 hiware c an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 an1106 translating assembly code from hc05 to st7 example drivers an969 st7 sci communication between the st7 and a pc an970 st7 spi communication between the st7 and e2prom an971 st7 i2c communication between the st7 and e2prom an972 st7 software spi master communication an973 sci software communication with a pc using st72251 16-bit timer an974 real time clock with the st7 timer output compare an976 driving a buzzer using the st7 pwm function an979 driving an analog keyboard with the st7 adc an980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 usb microcontroller an1041 using st7 pwm signal to generate analog output (sinusoid) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 software implementation of i2c bus master an1046 st7 uart emulation software an1047 managing reception errors with the st7 sci peripheral an1048 st7 software lcd driver an1078 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle an1082 description of the st72141 motor control an1083 st72141 bldc motor control software and flowchart example an1129 permanent magnet dc motor drive. an1130 brushless dc motor drive with st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1182 using the st7 usb low-speed firmware product optimization an982 using ceramic resonators with the st7 an1014 how to minimize the st7 power consumption an1070 st7 checksum selfchecking capability an1179 programming st7 flash microcontrollers in remote isp product evaluation an910 st7 and st9 performance benchmarking an990 st7 benefits versus industry standard an1086 st7 / st10u435 can-do solutions for car multiplexing an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f8 st72c171 151/152 12 summary of changes description of the changes between the current release of the specification and the previous one. revision main changes date 1.4 added figure 99 and figure 100 . oct-00 st72c171 152/152 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain sweden - switzerland - united kingdom - u.s.a. http://www.st.com |
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